1
A. Software
The TI 2401A DSP is made to do power inversion, so it
includes many registers to simplify the programming of sinetriangle PWM. A complete set of programming files used in
this project can be seen in Appendix G and on the attached
Hydrofly: Fuel Cell Project CD. TI’s Code Composer Studio
was used to develop the software and program the DSP.
Project files for Code Composer Studio and data sheets on the
TI 2401A DSP are also on the Hydrofly: Fuel Cell Project CD.
1) Overall Flow Diagram
The DSP software used in this design is based on a looping
switch statement as shown below in Figure 21. Initially, the
PWM State will be disabled, so the software will evaluate
Case 1 through Case 4 sequentially. The system will loop
through a given case until specified to move to a new state.
For example, the software will not move from Case 1 to Case
2 until specified in the Case 1 code. The software will
evaluate Case 1 through Case 4 a total of 180 times (30 sine
waves x 6 pulses per sine wave) before initializing the PWM
State. During the 180 loops, the system collects and averages
data for each of the six pulses and calculates the average half
period timing for each of the 3-phase signals. For each pulse,
the system will record the pulse width and the pulse-to-pulse
timing. After starting the PWM State, there is delay
programmed in to only start incrementally adding in DELTA
after 10sec. The same 10sec delay is used to keep the Fault
Check function, which shuts off the PWM in case of a fault,
inactive so the user can connect the interface to AMPS
without having to worry about the interface shutting off due to
the initial connection. If the Fault Check function were to be
active when connecting to the AMPS, the Zero Detection data
used in the Fault Check will usually see the shift caused by
switching in as a fault.
Start
System
Initialization
While (1)
Yes
Switch State
Case 1
Yes
Waiting for Pulse
sine-triangle PWM to be continually updated with the correct
sine values.
During a given loop in the switch statement, calculations
are always performed on the previous position on the pulse
stream. For HPTiming calculations, data from the previous
three pulses from the serial pulse stream are used.
2) Case 1 – Waiting For Pulse
In the “Waiting for Pulse” state, the system begins by
checking the Phase 1 Falling Edge Reference Signal for a
pulse to initially synchronize itself with the AMPS and
know what signal in the Serial Pulse Signal is the falling
edge of the first phase. Until the system is synchronized, no
other operation will be performed, and the system will
continually loop through this state. A very basic flow
diagram for this state can be seen below in Figure 22.
Once the system is synchronized, the system will
looks at the Serial Pulse Signal for a rising edge. When one
is found, several functions occur including:

Storing the Timer 2 Value in a variable which
represents the Pulse-to-Pulse time on the Serial
Pulse Signal.
 Stops, Resets, and Restarts Timer 2
 Increments Position Pointer in the array
By stopping and resetting the Timer, the variables stored for
the pulse wide and pulse-to-pulse timings already equal the
correct number, since we’re storing the ending value and
the starting value is 0. To prevent overflow in the timer,
Timer 2 increments every 4 CPU clock cycles. After
performing it various functions, it sets the next state, which
is to “Waiting For Falling Edge”.
The PWM Calculation/PWM Sync Check contains
some simple checks including:
 Initially starting the PWM only when system is
synchronized
 A simple PLL check that resets the sine wave to
keep it locked in with the AMPS
 A function that, when the PWM is active, sets the
system up to jump to the PWM State and then
return to the appropriate next state
Start
No
Case 2
Yes
Waiting for
Falling Edge
No
Case 3
Yes
Yes
Phase 1
Falling?
System Synced
Calculations
No
No
Case 4
Yes
Zero Crossing
Analysis
No
Case 5
Yes
Pulse Detected
and System
Synced?
PWM State
No
Record Times/Reset
Counters
Yes
No
Set Next State
Default
Figure 1 - Overall Software Flow Diagram
After the system has collected 180 pulses and
corresponding data, the PWM state is enabled. The system
continues to evaluate Case 1 through Case 4 in order, but will
begin to poll PWM State between Case 1/Case 2, Case 2/Case
3, etc. This polling allows the Compare Registers used in
PWM Calculations/
PWM Sync Check
Break
Figure 2 – Waiting for Pulse Flow Diagram
2
3) Case 2 - Waiting for Falling Edge
In the “Waiting For Falling Edge” state, the system is
looking for the falling edge of a pulse on the serial pulse
signal. When a falling edge is detected, the system will
record the time on Timer 2 for pulse width. A counter is
also decremented to prevent HPTiming calculations from
occurring before it has 3 previous pulses’ data to use for
calculations. The same PWM calculations/PWM sync
check is performed at the end of this state. A simple flow
diagram for the “Waiting For Falling Edge” state can be see
below in Figure 23.
Start
Calculate Pulse Width
Calculate Time
Between Pulses
Yes
Half Period?
Calculate Half Period
No
Set Next State
Start
Pulse
Ended?
PWM Calculations/
PWM Sync Check
Yes
Record Times
Break
No
Increment Position/
Decrement Counter
Set Next State
PWM Calculations/
PWM Sync Check
Break
Figure 3 – Waiting for Falling Edge Flow Diagram
4) Case 3 - Calculations
In the “Calculations” State, data from the previous pulse is
used to calculate and store the pulse width and pulse-topulse timing in an array for averages. The arrays are a 6
position area, one spot for each pulse location. When new
pulse widths are calculated, for example, the valued is
added to what is in the array position, and then will be
averaged later using a counter that keeps track of how many
data values are summed.
If enough data has been collect, the system will calculate
the HP Timing for the previous three pulses. Since there
are 6 pulses in the serial pulse stream, any three sequential
pulse give you the HPTiming for one of the phases. After
the HPTiming is calculated, the PWM Calculation/PWM
Sync Check is performed again. A flow diagram for the
“Calculations” State can be seen below in Figure 24.
Figure 4 – Calculations Flow Diagram
5) Case 4 – Zero Crossing Analysis
In the “Zero Crossing Analysis” state, the pulse width is
divided to get an estimate of the actual zero crossing. The
system will then decrement a counter that counts the number
of pulses received in the code. This counter is important as it
determines when the PWM will start. The system will then
perform a Fault Detection check by looking at the previous
pulse-to-pulse timing. If the data is outside the set values, the
system will shut off. After the HPTiming is calculated, the
PWM Calculation/PWM Sync Check is performed again. A
flow diagram for the “Zero Crossing Analysis” can be seen
below in Figure 25.
Start
Calculate Actual Zero
Crossing
Decrement Iteration
Counter
Yes
Detect Fault?
System Shutdown
No
Set Next State
PWM Calculations/
PWM Sync Check
Break
Figure 5 – Calculations Flow Diagram
6) Case 5 – PWM State
In the “PWM State”, the main function is to calculate the
values needed to create a reference sine wave and pass the
values to Compare Registers, which control the PWM
Outputs. When the DSP first enters this state, if enough data
has been taken, it averages the pulse width and pulse-to-pulse
time data.
3
The main calculations performed by the “PWM State” are
split into two sections: one part is calculated on the rising edge
of the triangle wave and on the other on the falling edge. On
the rising edge of the triangle wave, the inputs for the sine
lookup table are calculated for the three phases. These inputs
incorporate the relative position of the sine wave, DELTA
shift, transformer shift, and 120-degree phase shift, into the
calculation. The result is a number between –1 and 1 (input
range for sine lookup table) that is in Q15 format (multiply the
number by 2^15).
During the falling edge, the inputs are sent into the sine
lookup table and the outputs are converter back to a decimal
from Q15 format and then multiplied by a factor to set the
magnitude. The magnitude of each of the three phases is
controllable by the user. The PWM output is then turned on
and the counter which control the relative position of all the
reference sine waves in incremented.
In the PWM Calculations/PWM Sync Check section of this
state, the same functions as previously stated are performed
with one addition. There is a function that slowly increments
the DELTA after a 10-sec delay.
Start
Calculate
Timings/Update
Calculate Average
Carrier Frequency
Timings
No
Yes
Triangle Wave
Rising Edge?
Calculate/Load Sin
Positions in CMPR Registers
Calculate Phase Counts
Turn on PWM Output
Convert to Q15 Format
Increment Counters
Increment Counters
PWM Calculations/
PWM Sync Check
Break
Figure 6 – PWM State Flow Diagram
II. MANUFACTURING AND SUPPORT
A. Product Life Cycle Report
1) INTRODUCTION
a)
Hardware Components and General Interface Design
In order to transfer power from the Avista SR-12 hydrogen
fuel cell to the Analog Model Power System (AMPS), this
interface design uses four main components: a DC/DC
converter, DC/AC power inverter, Zero Detection Circuitry
(ZDC), and a delta to wye transformer. The interface does not
include the fuel cell. The DC/DC converter regulates and
steps up the DC output voltage from the fuel cell. This
regulated voltage is fed through a DC/AC power inverter to
create a three-phase AC signal at 60Hz. This three-phase
signal, which contains third harmonics from the switching of
the inverter, is filtered by a delta to wye transformer. This
transformer also steps up the AC voltage to an appropriate
magnitude, matched with the AMPS voltage. The final
component in the interface design is the zero detection
circuitry. This circuitry is used to determine the positions and
timings of the three voltage phases on the AMPS.
b)
Power Flow Control
The DSP used to operate and control the DC/AC power
inverter has been programmed to accept signals from the
ZDC. The DSP uses these signals to adjust the generated
voltage phase such that the signal from the inverter can be
synchronized with the voltage signals on the AMPS. Once
synchronized, the phase angle is adjusted to control the power
flow from the fuel cell to the AMPS, completing the interface
process.
c)
Protection
Protection schemes are located throughout the interface to
protect each of the components from damage. The DC/DC
converter contains input/output isolation, overvoltage
protection, current limiting protection, and short circuit
protection. The DSP on the DC/AC inverter monitors each of
the phases on the AMPS using the ZDC. If there is a sudden
change in frequency on any of the phases, the DSP will
quickly stop the inverter from generating the three-phase
signal. This prevents possible current spikes or other
unwanted transients from occurring. Fuses were placed after
the DC/AC power inverter for protection in case of a current
spike. The ZDC also contains protection. An optocoupler
isolates the analog input circuitry from the output that
connects to the I/O pins on the DSP. This isolation prevents
current spikes from damaging the DSP.
2) Design
a)
Selection of Hardware Components
The fuel cell used in this design is capable of reliably
providing 100W of power. In order to provide a certain level
of device safety and upgradeability, the DC/DC converter was
chosen to have a power rating of 200W. This specification
also helps ensure that the current ratings on the device won’t
be exceeded due to reactive power transferred through the
interface. The DC/AC power inverter, obtained from Tier
Electronics, has 600V IGBTs for switching rated at 3A RMS
at 5kHz and 2A RMS at 10kHz with a peak current of 6A. The
transformer, obtained from the UI ECE department, is rated at
8.5kVA and was chosen because of its availability in the lab.
The ZDC was built from the ground up to meet this system’s
specifications. It utilizes an op amp with active feedback and
a several logic gates to output a series of pulses that can be
interpreted by the DSP to determine the inverter switching
timings.
b)
Software Programming and System Control
In order to allow the DSP to adjust the inverter output
voltage and phase, it was reprogrammed. The reprogramming
4
process involved analyzing the current programming,
modifying it to adjust the voltage magnitude, and adding
additional code to accept the input from the ZDC. The
software used to accomplish this task was the TI Code
Composer Studio.
c)
Hardware and Software Costs
Once appropriate components were chosen for this design,
the DC to DC converter, the inverter, and the components
used to create the ZDC were all purchased with funding from
the ECE department power lab budget and the Corbit Senior
Design Fund. The TI Code Composer Studio and J-TAG
emulator used to program the DSP were donated by TI. The
three-phase transformer and inductor bank are the property of
the ECE department, and will serve as removable, standalone
devices that are easy to connect and disconnect. These items
were provided at no cost.
3) Implementation and Testing
a)
Component Testing
Each of the four components were individually tested for
their input/output relationship. A major factor in component
testing is correcting problems with the individual components
in the implementation stage. As expected in the prototype
design, the implementation stage has a high probability of
errors in its early stages. The DC/DC converter was tested to
see how much the output voltage varies over the entire input
voltage range. The inverter accepted artificial ZDC signals
from a function generator to generate a pulse width modulated
voltage signal before the actual ZDC was implemented. The
transformer was tested for leakage reactance and input/output
voltage characteristics. The ZDC was tested first with low
voltage signals, then with the actual voltage signals from the
AMPS. The output of the ZDC showed the pulse sequences
sent to the DSP I/O pins.
c)
d)
Release Plans
The interface will be a package that consists of: a DC/DC
converter, a DC/AC inverter, three-phase zero detection
circuitry board, three single phase transformers, inductors,
cables for connections between components, a DSP software
package, and complete documentation in both paper and
electronic format. The supplied documentation will outline
each part of the interface, troubleshooting techniques, PCB
construction, safety and operation methods, and maintenance.
This interface will be used solely for power system research
and education, so the system is set up to be adaptable and/or
upgradeable to changing needs. This documentation will
include contact information should any issues or problems
arise and require the attention of the original designers.
Component Implementation
The components implemented in this project can be viewed
as one of two types: commercially manufactured or designed
from the ground up. Each component serves an individual
function in the interface design and works together with the
other components to create a fully functional system. The
DC/DC converter takes a variable DC input voltage and
outputs a constant DC voltage. The implementation of the
inverter was more involved since it needs to control the power
flow and isn’t just a black box that functions as desired. For
this reason, its implementation requires more time and effort
to prevent possible functionality problems. The transformer is
also a pre-manufactured component, providing the final
connection to the AMPS. The zero detection circuitry was
designed and assembled from the ground up. It has been
implemented on a printed circuit board to organize its
functionality and finalize its design.
b)
and goals. Extensive interface testing was not needed to meet
these goals. In addition, the usage of this product will not be
frequent enough and the operating conditions will not be
stressful enough justify rigorous testing of this design.
Interface Testing
Connecting the four main components together made the
completed interface ready for testing. The goal of the
interface testing was to meet the basic project requirements
4) Maintenance
a)
Zero Detection Board
The interface requires occasional maintenance. Most of the
maintenance will involve replacing parts on the zero detection
circuit PCB board as they age. The time between this
maintenance will be greatly dependent on the amount of time
the system is in use. The ECE department will have complete
documentation on the zero detection circuitry and PCB board
to provide easy maintenance or construction of new boards
should it be required.
b)
Software
Other maintenance will include DSP software updates to fix
any bugs or flaws in the programming. These bugs could arise
under abnormal conditions when tests are being performed on
the AMPS or under normal conditions because of aging
components. There may also be bugs in the release software
that were not found during final testing. Every effort has been
made to ensure durability of the system in case there is a
problem within the interface design. TI provides extensive
documentation on the DSP used in the DC/AC inverter; this
documentation will be included in the final design package.
c)
Other
Maintenance on the DC/DC converter and DC/AC inverter
will require contact with appropriate vendors for support. The
DC/DC Converter includes a twelve-month warranty, subject
to application within good engineering practice.
5) End of Life
This interface, while designed for use with a hydrogen fuel
cell, is capable of providing an interface from any alternative
energy source or other power source to the AMPS, as long as
it does not exceed the specifications of the interface. In the
case that the hydrogen fuel cell it was designed for is worn
beyond feasible repair, this interface will still be useable in
other energy supply research or education. As time passes, the
5
world’s power requirements have been ever increasing. With
the design of this system, individual components can be
replaced or upgraded to modify the overall specifications of
the interface and prolong its life cycle. This interface will
become obsolete when all alternative sources exceed the
specifications and capabilities of this interface or when parts
become expensive or impossible to repair.
The life of the system is also somewhat dependent on the
availability of software to communicate with the TI DSP. The
current programming software requires the Windows
operating system to function. Without the necessary software,
it will be impossible to communicate with the DSP and
provide updates to the code.
6
3) Failure Modes and FMECA Analysis
B. Hardware Reliability Analysis
1) INTRODUCTION
This multi-faceted report provides a reliability analysis for
the interface created to provide power to the Analog Model
Power System (AMPS) from an Avista SR-12 fuel cell. The
interface consists of four main parts: a DC/DC converter,
DC/AC inverter, Zero Detection Circuitry (ZDC), and a
transformer. This analysis provides a list of possible failure
modes, an examination of the Mean Time Between Errors
(MTBF) for each of the components in the interface, and a
Failure Mode and Effects Criticality Analysis (FMECA). This
reliability analysis is important in the design of any new
product. It can be used to plan the operation of the interface
around its product and individual component life expectancy.
It also helps with troubleshooting since it provides information
regarding which components are more likely to fail first.
2) System Failure Rate Calculations
The overall failure rate of the system was calculated using
the Relex Analytical Tools, component failure rate data, and
Microsoft Excel. The Relex Analytical Tools and component
failure rate data were used to find the average failure rate for
each of the components in our system for every 10 9 hours of
operation. The average component failure rate information
was entered into Excel to calculate the MTBF for each of the
subsystems, individual components, and the interface as
whole. To find the total MTBF for our system, each
components was weighted based on the number of
components of that type in the entire interface and then took
the sum of the MTBF of each of the subsystems. Through the
research performed, it was difficult to find exact failure rate
data for all components. When exact failure rate data could
not be found, similar components were used to estimate a
reasonable failure rate of each component.
The interface design is divided into five main subsystems:
DC/DC Converter, DC/AC Inverter, Transformer, Fuses, and
ZDC. The DC/DC converter and DC/AC inverter are
packaged subsystems purchased for the interface. The ZDC is
comprised mainly of an op amp circuit utilizing resistors,
feedback capacitor, supply voltage source, switching
transistor, optoisolator, and output logic gates to produce the
necessary output signals. Table 1 illustrates the results of the
MTBF calculations.
TABLE 1. MTBF GRAPH - OVERVIEW
Total
Failure
Number of
Component
Failure
Rate
Components
Rate
DC/DC Converter
0.0028
1
0.0028
DC/AC Inverter
0.041
1
0.041
Transformer
Percent of
Total
Failure Rate
0.36
5.25
0.013
1
0.013
Fuses
0.00015
3
0.00045
0.06
ZDC
0.7244
1
0.7244
92.67
Total MTBF (hours)
1.66
a)
Potential Failure Modes
The components used in the design of this system have the
potential for failure at some point in their lifecycle. User error
or non-ideal operating conditions are also likely to occur. The
following table lists these potential failure modes. These
failure modes focus on the individual subsystems, the user,
and the operating conditions present during system operation.
TABLE 2. POTENTIAL FAILURE MODES
1.
Internal Component Failure
2.
Improper Use
3.
Physical Damage
4.
AMPS noise/transients
5.
DSP Software Failure
6.
Insulation Failure
7.
Reverse Power Flow
8.
Thermal Shock
9.
DC Input Voltage
10. Protection Circuitry
11. External Component Failure
12. Excessive Loading
b)
Ratings
(1)
Risk Priority Number
Each of the items in Table 2 has been given a Risk Priority
Number (RPN) based on its severity, occurrence, and
detectability. To determine the RPN, each category was
assigned a severity, occurrence and detection rating (1-10).
These ratings are multiplied together to calculate the RPN. A
higher RPN means that the failure mode is more likely to
cause a system-wide problem or safety issue. The method for
determining the ratings is discussed in detail in the remainder
of this section. All ratings and RPNs for the potential failure
modes are listed in Table 3 at the end of this section.
(2)
Severity
The severity rating for each potential failure mode was
based upon how much damage would be caused if the failure
mode occurred. A high severity rating indicates a failure that
would cause irreparable damage or would require component
replacement or expensive design alterations. A high severity
rating may also indicate a significant safety risk associated
with the failure mode. A low severity rating indicates little to
no damage or possibility of damage to the system.
(3)
Occurrence
The occurrence rating indicates the likelihood of entering
into a potential failure mode. A low occurrence rating
indicates that the failure mode may never occur, and a high
rating indicates that the failure mode may occur frequently.
1279344975
(4)
Detectablilty
7
The detection rating indicates how difficult it would be, in
the event of a system failure, to detect a given failure mode. A
high rating indicates that it would be impossible to detect a
failure mode without a meticulous system analysis. A low
rating indicates that a failure mode would be easily detected
by the system operator.
TABLE 3: FMECA TABLE OF RATINGS
Internal Component
Failure
Improper Use
Severity
Occurrence
Detection
RPN
10
3
9
270
7
6
3
126
Physical Damage
AMPS
noise/transients
DSP Software
Failure
Insulation Failure
Reverse Power
Flow
Thermal Shock
9
7
2
126
5
6
4
120
5
4
5
100
9
1
10
90
7
2
6
84
6
2
5
60
DC Input Voltage
5
9
1
45
Protection Circuitry
External Component
Failure
Excessive Loading
6
2
3
36
4
8
1
32
5
2
2
20
4) Conclusion
A hardware reliability analysis helps determine which
subsystems in the fuel cell/AMPS interface are most likely to
encounter problems: ZDC, DC/AC Inverter, DC/DC
Converter, or transformer.
With this FMECA, the most probable failure modes could be
determined. The top three failure modes, as seen in the
FMECA Table 2, are internal component failures, improper
use of the interface, and physical damage to the system. Since
the purpose of the reliability analysis report is to supply the
design group with an idea of where potential failures will
occur, design adjustments can be made to improve the design
reliability by using the results of the FMECA.
Based on this report, the following design
adjustments have been made to reduce the risk of a system
failure:
1. Use a system enclosure to prevent physical damage to the
system.
2. Minimize improper use by supplying a well-written
operation manual.
Other adjustments, though out of the scope of this project,
may be made to further reduce the RPN for specific failure
modes.
This FMECA should be used to determine how to achieve a
more reliable system and understand where reliability issues in
the system will occur.
III. BUDGET
Table X shows a summary of our project budget. A more
detail Budget/Bill of Material can be seen in Appendix X.
TABLE 6 – BUDGET SUMMARY
Item
DC/DC Converter
Predicted Cost Actual Expenditures
$318.00
$398.00
DC/3-Phase AC Inverter
$500.00
Hydrogen
$45.00
Poster/Report Binding
$70.00
Protection Circuitry
$50.00
Filtering (Inductor Bank)
$50.00
Transformer
$125.00
Printed Circuit Boards
$350.00
Circuit Components
$150.00
Utility Cart
$100.00
Miscellaneous
$300.00
Code Composer Studio
$495.00
XDS510PP-Plus Parallel Port Emulator
$999.00
Total Predicted Budget
Total Expeditures
Total Budget Left
$500.00
$65.00
$102.30
$28.80
Donated
Donated
$180.00
$159.96
$58.00
$0.00
Donated
Donated
$3,552.00
$1,492.06
$2059.94
8
Appendices
9
Appendix A – Absopulse BAP265 Series
DC/DC Converter Data Sheet
10
11
Appendix B – Tier Electronics
DC/AC Inverter I/O Pins and Pinouts
12
DC Power In
J2 and J3 are DC power in
AC Power Out
J1 is AC out 1 (Controlled by DSP pin 27 and pin 10)
J5 is AC out 2 (Controlled by DSP pin 11 and pin 28)
J6 is AC out 3 (Controlled by DSP pin 29 and pin 12)
Communications Board (Connecter J7)
Pin 1 = 15V
Pin 2 = RX (goes to DSP pin 2)
Pin 3 = TX (comes from DSP pin 3)
Pin 4 = Data in line (goes to DSP pin 31)
Pin 5 = Data out line (comes from DSP pin 22)
Pin 6 = Aux 1 (goes to DSP pin 15)
Pin 7 = Aux 2 (goes to DSP pin 14)
DSP pin 32 is controlled by Q1 pin 3(of the main board with the heatsink on it)
13
Appendix C – Zero Crossing Circuit
Feedback Derivation
14
15
16
Appendix D – Zero Detection Circuitry
Simulation Results
17
18
19
20
21
22
23
Appendix E – Zero Detection Circuitry
PCB Board Design, Parts/Build List
24
25
26
27
28
29
Appendix F – Zero Detection Circuitry
Test Point Reference
30
______________________________________________________________________
Test Point Locations (Labeled on PCB Board)
TP(X) – X
Phase(1,2,3)
Test Point Location Location Number
______________________________________________________________________
Pin Assignments (Refer to Schematic Above)
TP(X) – X
Circuit(1,2)*
Phase(1,2,3)
*Circuit = 1 refers to ZDC that triggers at +0.7V
Circuit = 2 refers to ZDC that triggers at -0.7V
For each phase, the +0.7V circuit is above the –0.7V circuit
31
Test Point Reference is oriented as if you were looking down on the
PCB board with the Phase 1,2,3 inputs on your left, and +/- Vcc
inputs top.
TP(x)-1
VOOP(1)-x
GND
V+(1)-x
V-(1)-x
32
GND
V-(2)-x
VOOP(2)-x
V+(2)-x
TP(x)-2
VIISO(1)-x
GND
TP(x)-3
VIISO(2)-x
GND
33
TP(x)-4
GND
VIXOR(1)-x
GND
VIXOR(2)-x
TP(x)-5
Not shown on schematic above. It gives you the output of the XOR Gate.
GND
XORx
TP(x)-6
Not shown on schematic above. It gives you the output of the Inverter Gate.
INVx
GND
34
Appendix F – DSP Software