Homework 3 solutions

Homework 3 solutions
EE155/255 Green Electronics, Fall 2016
Problem 1
This problem was intended to help gain familiarity with LTspice as a circuit simulation tool, and to give
intuition about the operation of a solar panel while maximum power point tracking.
Spice deck used:
Explanation: This plot shows the full transient for the boost converter running at a DF (upper FET) of
0.63. From our periodic steady state analysis of the boost converter, the voltage difference should be
1/D, so we expect the output/input voltage ratio to be 1/0.63 = 1.59. The converter boosts voltage from
about 31.5V to 47V for a ratio of 1.49, which corresponds pretty well. Note that the DF we put into the
half bridge driver is not exactly the same as the DF of the switches themselves, because the half-bridge
driver will distort the DF by, for example, adding dead time between the switch on-states to prevent
shoot-through current. If we take into account the DF distortion from the half-bridge driver, the boost
ratio agrees with the results from the periodic steady state analysis.
Explanation: This plot shows a close-up of 5 switching cycles of the boost converter after it has reached
periodic steady state. Notice the inductor current (3rd plot, green) is following the standard sawtooth of
charging and discharging. The sawtooth is very linear because the capacitors have kept the voltage on
either side quite stable, so our common simplification that the input and output are “voltage sources” is
quite a good approximation. Notice that the load (output) voltage in the second plot (red trace). The
waveforms follows a standard charge/discharge curve, with one unique feature: the voltage dips
suddenly at the end of the charging period. This implies a sudden release of current from the output
capacitor, and we will soon recognize that this is due to the slow reverse recovery time of the top diode.
Problem 2
This question involved using spice’s .meas commands to calculate important information about a
waveform. Additionally, the problem helps illustrate where switching losses come from in power
converters, and especially the insidious effect of reverse recovery time in diodes.
The spice deck used for the following waveforms is the same as that presented in problem 1, with the
addition of these .meas commands.
fet_loss_upper: INTEG((v(vl)-v(mid))*(ix(hb:fh:1)))=5.9419e-005 FROM 0.000247
TO 0.00024712
fet_loss_lower: INTEG(v(mid)*(ix(hb:fl:1)))=3.68421e-005 FROM 0.000247 TO
0.00024712
fet_loss_upper_2: INTEG((v(vl)-v(mid))*(ix(hb:fh:1)))=-1.1907e-006 FROM
0.00025036 TO 0.00025058
fet_loss_lower_2: INTEG(v(mid)*(ix(hb:fl:1)))=2.5616e-005 FROM 0.00025036 TO
0.00025058
Results in table
Event
Top FET turn-off
Top FET turn-on
Top FET loss
59uJ
-1uJ (negligible)
Bottom FET loss
37uJ
26uJ
We can see that the major switching losses come from the turning off of the top FET. Turning on the top
FET cases very little loss in comparison. The waveforms for these two switching events are on the next
page.
Explanation: This trace shows the switching waveforms during the turn off of the upper FET. In the top
plot, we have in blue the lower FET loss, and in green the upper FET loss. Note the incredibly high
instantaneous currents and powers immediately after the start of the switching event. The huge spike
in current (shown in the bottom plot) is due to the reverse recovery of the top diode. While physical
circuits will see a spike, the sharpness of the spike (the “hardness” of the recovery) seen as the very
sudden drop in current on the right side of the spike is a simulation artifact. The diode takes ~15ns to
turn off, and during this time the majority of the switching losses in the lower FET occur. The second
bump in current is an “echo” of the first spike caused by parasitic inductance in the path from Vdd to
GND, so a portion of the energy lost due to reverse recover comes late. Note that the second bump in
current plays a very small role in the lower FET turn off losses, because by this time the voltage across
the lower FET (Vmid) has fallen to nearly zero, but does impact the upper FET losses, since voltage
between Vd and mid has risen. While the .meas statement above correctly measure the switching
transient energy, you can also measure switching energies directly from the spice viewer by holding
control while clicking on the waveform title.
Explanation: The top FET turn-on event is somewhat less exciting. The top FET itself incurs almost no
losses during this event, as the parasitic body diode of the FET turns on when current decreases in the
bottom FET, so the switching occurs after the voltage is nearly zero. On the other hand the bottom FET
which must interrupt the current flow takes a reasonable hit, as the voltage across it must increase to
the output voltage while nearly the full current is still running through it. However, note it is not hit
with the spike of reverse recovery current, which leads its switching loss while turning off to be lower
than its loss while turning on.
Problem 3:
Explanation: In part 3, we examine the transient response of the boost converter during a sudden shift
in duty factor. As expected, moving the high FET from 0.9 to 0.5 DF increases the voltage at the output,
and increases the inductor current as well. We can see that the circuit has very little damping, and in
the absence of a controller, the oscillations ring out for a very long time. The length of these oscillations
can be described as the circuit having a low damping factor “zeta” or a high quality factor “Q”. As we’ve
seen in our control theory lectures, we can add controllers to the system to change the damping factor
and greatly decrease or eliminate this ringing.
Note: Inductor current from ~4 to ~8 amps. Note the larger inductor current swings when at 0.5DF than
0.9DF. Output voltage moves from ~38V to ~42V, but input voltage moves from 36 to 22V. Note that
the input voltage changed much more substantially than the output. This may be surprising, because
we often think of a voltage converter as generating an output voltage. Here, the output voltage is not
controlled, and the load is merely a resistor, so it is free to swing. Additionally, the input power source,
the PV panel, is not a (roughly) constant voltage source, like many other converters that operate based
on battery or wall power.