Improving Placement
under the Constant Delay Model
Kolja Sulimma1, Ingmar Neumann1, Lukas Van Ginneken2, Wolfgang Kunz1
1EE
and IT Department
University of Kaiserslautern
2Magma
contact: [email protected]
Design Automation
Cupertino, CA, USA
Overview

Conventional Delay Models



Constant Delay Model




detailed vs. abstract delay models
timing driven placement and the critical path problem
introduction
placement under the constant delay model
fast and exact area computation
Experimental Results
2
Delay of a CMOS Gate


non-linear
depends on many variables





load capacitance
input slew rate
temperature
supply voltage
interconnect




gate delay
resistance
crosstalk
inductance?
detailed tabular models can
be used for timing analysis

to irregular to guide the
synthesis process
load capacitance
3
Unit Delay Model

assumes all gates have the
same delay



independant of load, etc.
performes astonishingly well
not accurate enough in the
deep sub micron age
unit delay model
gate delay
load capacitance
4
Linear Delay Model




linear delay/load dependancy
relatively accurate fit
widely used for timing driven
tool flows
linear slew effects are
commonly added to improve
the model
linear delay model
gate delay
load capacitance
5
Placement with Linear Delay Model


arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
tcritical
6
Placement with Linear Delay Model


arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
tcritical
7
Placement with Linear Delay Model


arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
tcritical
8
Placement with Linear Delay Model


arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
tcritical
9
Placement with Linear Delay Model


arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
tcritical
10
Placement with Linear Delay Model



arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
delay of the gate and predecessors changes trivially


tcritical
11
Placement with Linear Delay Model



arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
delay of the gate and predecessors changes trivially


tcritical
12
Placement with Linear Delay Model



arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
delay of the gate and predecessors changes trivially


tcritical
13
Placement with Linear Delay Model



arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
delay of the gate and predecessors changes trivially


tcritical
14
Placement with Linear Delay Model




arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
delay of the gate and predecessors changes trivially
but what about the critical path?


?
tcritical
15
Placement with Linear Delay Model




arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
delay of the gate and predecessors changes trivially
but what about the critical path?


?
tcritical
16
Placement with Linear Delay Model




arrange gates of fixed area to minimize the circuit delay
moving a gate modifies the length (and capacitance) of
adjacent wires
delay of the gate and predecessors changes trivially
but what about the critical path?


?
tcritical
17
Placement with Linear Delay Model

linear time needed to update circuit delay after cell move


common workarounds:



prohibitively slow
optimisation of secondary criteria (e.g. wire length)
heuristical net weights based on „criticality“ of the net
weights become stale after multiple moves

increasingly inaccurate information about circuit delay
?
tcritical
tcritical
18
Constant Delay Model



the models presented so far modeled the delay of a given
gate implementation of constant size
Constant Delay Model models the gate size required to
meet a given constant gate delay
requires a cell library that provides many cell sizes for
each logic function it implements, or a cell that allows to
size cells continously
19
Constant Delay Model

the delay of a gate is assumed to be
constant
modeled delay
load capacitance
20
Constant Delay Model


the delay of a gate is assumed to be
constant
for any load capacitance a certain gate
size is required to achieve this delay
modeled area
modeled delay
load capacitance
21
Constant Delay Model


the delay of a gate is assumed to be
constant
for any load capacitance a certain gate
size is required to achieve this delay
this gate size ideally depends linearly
on the load capacitance
modeled area
modeled delay
A

C
load capacitance
22
Constant Delay Model




the delay of a gate is assumed to be
constant
for any load capacitance a certain gate
size is required to achieve this delay
this gate size ideally depends linearly
on the load capacitance
if there is only a fixed set of gate sizes
the actual area will deviate from the
model
actual area
modeled area
modeled delay
load capacitance
23
Constant Delay Model





the delay of a gate is assumed to be
constant
for any load capacitance a certain gate
size is required to achieve this delay
this gate size ideally depends linearly
on the load capacitance
if there is only a fixed set of gate sizes
the actual area will deviate from the
model
this causes the actual delay to deviate
from the model
actual area
modeled area
actual delay
modeled delay
load capacitance
24
Constant Delay Model






the delay of a gate is assumed to be
constant
for any load capacitance a certain gate
size is required to achieve this delay
this gate size ideally depends linearly
on the load capacitance
if there is only a fixed set of gate sizes
the actual area will deviate from the
model
this causes the actual delay to deviate
from the model
fortunately, this effect is alleviated by
load effects on the preceeding gates
actual area
modeled area
actual delay including preceeding stage
modeled delay
25
Constant Delay Model: Placement

find a placement minimising the circuit area for a given circuit delay

note:



ideally all cells remain critical during the placement process
avoids critical path problem
we propose a new approach based on net weights that



measure exactly how a local change of the wire capacitance effects the
overall circuit area
can be computed efficiently in advance
remain valid throughout the placement process
26
Constant Delay Model: Circuit Area


gate area Ai increases linearly with the load capacitance Ci seen
at gate i.
Ai  Ci 
Ai
Ci
i
i
27
Constant Delay Model: Circuit Area


the input capacitance Cij of any input j of gate i increases linearly
with the load capacitance
C
Cij  Ci  ij
Ci
j
i
28
Constant Delay Model: Circuit Area

this in turn increases the area Aj of the predecessor gate linearly
j
j
i
29
Constant Delay Model: Circuit Area



this in turn increases the area Aj of the predecessor gate linearly
as a result a capacitance change at a node causes a linear
increase in area on all predecessor gates
A j
A j
Cij
A j  Ci 
 Ci 

Ci
Cij
Ci
j
j
i
30
Constant Delay Model: Circuit Area

the total circuit area A



is the sum of all gate areas Ai
changes linearly with Ci
A   Ai  Ci 
j
j
A j
Ci
i
j
j
i
31
Constant Delay Model: Circuit Area

the total circuit area A



is the sum of all gate areas Ai
changes linearly with Ci
A   Ai  Ci 
j
j
A j
Ci
A
global area
Ci sensitivity
i
j
j
i
32
Area Sensitivities and Placement




area of the circuit and the individual gates may change during the
placement process, but the area sensitivity never does.
area sensitivities allow to accurately compute the effect of a cell
move on circuit area for a gate move
placer can directly optimise circuit area without heuristic weights
we only know the size of the overall circuit but not the sizes of the
individual gates or partitions. This can introduce small inaccuracies
in the wire length calculation.
33
Area Sensitivities
area sensitivities for all gates can be computed in advance:
 linear sweep for combinational circuits
 inversion of a sparse matrix for sequential circuits
34
Area Sensitivities
area sensitivities for all gates can be computed in advance:
 linear sweep for combinational circuits
 inversion of a sparse matrix for sequential circuits
 details are shown in the paper
 Ci 0i  n
 Ci 0i  n


A  c   i
 A*   ( D  I )1  ( w  c *)   i
 A*


A
A

A
Ci
 
j

A j
(D  I ) 
C
1
j
ij
35
Experiments



existing timing driven toolflow was modified to support the constant
delay model
original flow used for comparison
both flows use




FM-based recursive bipartitioning
half perimeter wire length estimate
technology mapping for hypothetical cell generator for arbitrary seriesparallel CMOS cells
designer choses target delay from area/delay tradeoff curve
36
Conventional
Timing Driven Flow
Proposed Constant Delay
Based Flow
Technology Mapping & Gate Sizing
Technology Mapping & Gate Sizing
gate delay:
gate area:
circuit delay:
circuit area:
gate delay:
gate area:
circuit delay:
circuit area:
f(C)
fixed
unknown
known approx.
fixed
f(C)
fixed
unknown
Preprocessing
timing not met
computation of area sensitivities
Placement
(Recursive Partitioning)
Placement
(Recursive Partitioning)
heuristic edge weighting
wire length updates
cut cost estimates circuit delay
cut cost accurately reflects
circuit area
static timing analysis
computation of partition sizes
37
Experimental Results
Circuit
C432
C499
C880
C1355
C2670
C3540
C5315
C6288
C7552
Target Conventional
Proposed
Delay Area Delay Area Delay
1.80 6.34
1.81 5.87
1.81
1.64 17.5
1.66 15.0
1.68
1.50 12.8
1.50 10.3
1.48
2.10 20.9
2.08 19.5
2.09
1.20 26.7
1.21 22.1
1.26
2.73 49.2
2.74 36.2
2.74
3.00 70.2
3.03 56.4
3.03
1.18 83.0
1.18 82.8
1.17
2.60 89.0
2.56 75.9
2.59
375,6
324,1
118%
100%
C7552
C6288
C5315
C3540
C2670
C1355
C880
C499
C342
38
Conclusion


we exploit properties of the constant delay model to simplify and
improve the placement process
the exact area costs of a cell move can be calculated based on
area sensitivities

15% area improvement compared to conventional approach

computationally efficient
39