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UC San Diego Computer Engineering
Calibrating Achievable Design
September 2003
VLSI CAD Laboratory
Puneet Gupta, Andrew B. Kahng
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Delay (+k)
Cycle Time
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Selling point delay
Die Area
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Total cost of OPC
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UC San Diego Computer Engineering
VLSI CAD Laboratory
• Use off-the-shelf synthesis tool, along with yield
library similar to timing libraries (e.g., .lib) to
perform OPC “sizing” operation via mapping
shown at left
• Pessimism ensured via extreme order statistics
• We generate a library similar to Synopsys .lib with (+3) delay
values for various output loads.
• We characterize for yield a subset of the Artisan TSMC 0.13m
standard-cell library. An example is given below.
No OPC
Aggressive OPC
• RETs increase mask feature complexities and
hence mask costs: the 130nm technology
node brings on the “million-dollar mask set”
Type of OPC
Leff (nm)
3 of Leff
Figure Count
Aggressive
130
5%
5X
Delay (, 3) for
NAND2X1
(60.7, 2.14)
• The average mask set produces only 570
wafers  amortization of mask cost is difficult
Medium
130
6.5%
4X
(60.7, 2.80)
No OPC
130
10%
1X
(60.7, 4.33)
Experiments and Results
Design Normalized Cost
• We need Design for Value (DFV) methodology
to achieve required parametric yields ($/wafer)
while minimizing the total of all costs incurred
“alu128” 5.0 (Aggressive OPC)
O(25 mask levels) ~ “$1M mask set” in 130nm
MinCorr: The Cost of Correction Problem
Normalized Selling
Point Delay
0.9479
4.0 (Medium OPC)
0.9623
1.0 (No OPC)
1.0000
1.6038
0.9479
1.3751
0.9857
• Synopsys Design Compiler used for synthesis
• Figure counts, critical dimension (CD) variations
derived from Numerical Technologies OPC tool
• Small (4%) selling point delay variation between
max- and min-corrected versions of design
• Sizing-based optimization achieves 65%
reduction in OPC cost without sacrificing
parametric yield
Sample results on a 8064-gate combinational design
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Can modify conventional performance optimization methods to solve the MinCorr problem; we use an off-theshelf synthesis tool to achieve up to 77% cost reduction compared to aggressive OPC, without increasing
selling point delay
Publications
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OPC is more of a manufacturability issue than a performance or yield issue
Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, “Design Sensitivities to Variability:
Extrapolation and Assessments in Nanometer VLSI”, Proc. IEEE ASIC/SoC Conf., Sept. 2002, pp. 411415.
• D. Sylvester, P. Gupta, A. B. Kahng, and J. Yang, “Toward Performance-Driven Reduction of the Cost of
RET-based Lithography Control” (Invited Paper), SPIE Conf. on Design and Process Integration for
Microelectronic Manufacturing, Feb. 2003, to appear.
• P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, “A Cost-Driven Lithographic Correction Methodology
Based on Off-the-Shelf Sizing Tools”, Proc. ACM/IEEE Design Automation Conf., 2003, pp. 16-21.
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Our ongoing research pursues:
• Applying selective OPC at a finer granularity than gates: Tolerable “Edge Placement Errors” per feature can
be calculated and used by the OPC tool.
• Alternative MinCorr solution approaches based on transistor sizing and cost based delay budgeting methods
• Including interconnect variation in the analysis
• Making the yield library input slew-aware
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UC San Diego Computer Engineering
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• Statistical static timing analysis (SSTA) based correction flow
UC San Diego Computer Engineering
UC San Diego Computer Engineering
Function-aware OPC can reduce total cost of OPC while still meeting cycle time and yield constraints
UC San Diego Computer Engineering
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VLSI CAD Laboratory
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VLSI CAD Laboratory
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Conclusions and Future Work
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UC San Diego Computer Engineering
Many features in layout are not timing critical  more process variation may be tolerable for them
Less-aggressive OPC  lower costs (reduced figure counts, shorter mask write times, higher yields)
Printability of the design  a certain minimum level of OPC is required
Define the selling point as the circuit delay which achieves 99% parametric yield 
The MinCorr problem seeks a level of correction for each layout feature such that a prescribed
selling point delay is attained with minimum total cost of corrections.
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• Monte-Carlo simulations, coupled with linear interpolation, are used
to estimate delay variance given the CD variation
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UC San Diego Computer Engineering
Nominal Delay
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MinCorr
Cost of correction
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UC San Diego Computer Engineering
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UC San Diego Computer Engineering
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VLSI CAD Laboratory
Gate Sizing
Cell Area
• Assume perfect correlation of variation along all
paths  resulting linearity allows propagation of
(+3) or 99% delay to primary outputs using
standard Static Timing Analysis (STA) tools
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VLSI CAD Laboratory
VLSI CAD Laboratory
UC San Diego Computer Engineering
UC San Diego Computer Engineering
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VLSI CAD Laboratory
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UC San Diego Computer Engineering
UC San Diego Computer Engineering
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• Mask cost is assumed proportional to number of layout features
• Mask writers work equally hard to perfect
critical and non-critical shapes; errors found in
either during mask inspection will cause the
mask to be discarded
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VLSI CAD Laboratory
Yield Aware Library Characterization
Trends in Mask Cost
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UC San Diego Computer Engineering
As minimum feature sizes continue to shrink, patterned features have become significantly smaller than the
wavelength of light used in optical lithography. As a result, the requirement for dimensional variation control,
especially in critical dimension (CD) 3sigma, has become more stringent. To meet these requirements, resolution
enhancement techniques (RET) such as optical proximity correction (OPC) and phase shift mask (PSM) technology
are applied. These approaches result in a substantial increase in mask costs and make the cost of ownership (COO)
a key parameter in the comparison of lithography technologies. To properly calibrate the cost-benefit analysis of
alternative lithography strategies, it is necessary to first understand the concept of design-aware, minimum-cost
correction to achieve given parametric yield.
No concept of function is injected into today's mask flow. That is, current OPC techniques are oblivious to the design
intent, and the entire layout is corrected uniformly with the same effort. We propose a novel minimum cost of
correction (MinCorr) methodology to determine the level of correction for each layout feature such that prescribed
parametric yield is attained. We highlight potential solutions to the MinCorr problem and give a simple mapping to
traditional performance optimization. We conclude with experimental results showing the achievable RET cost
savings while attaining a desired level of parametric yield
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VLSI CAD Laboratory
UC San Diego Computer Engineering
Abstract
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VLSI CAD Laboratory
Solving MinCorr: An Analogy to Gate Sizing
Annual Review
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UC San Diego Computer Engineering
UC San Diego Computer Engineering
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VLSI CAD Laboratory
VLSI CAD Laboratory
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UC San Diego Computer Engineering
A Cost-Driven
Lithographic Correction Methodology
Based on Off-the-Shelf
Sizing Tools
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VLSI CAD Laboratory
UC San Diego Computer Engineering
VLSI CAD Laboratory
UC San Diego Computer Engineering
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