Exercise Manual
for
Analyzing Designs Using the Mentor
Graphic’s ModelSim-Altera Simulation Tool
Software and Hardware Requirements to Complete All Exercises
Software Requirements: Quartus II 6.0; ModelSim 6.1d
Hardware Requirements: None
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
2
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Exercise 1
3
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
4
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Exercise 1
Objectives

Understanding ModelSim basic simulation steps
 Creating Library(s)
 Compiling Verilog & VHDL
 Starting Simulation
 Advancing Simulation
Note: This lab exercise contains design files in both Verilog and VHDL. These
instructions are for both. Please choose the HDL language with which you are
more comfortable. The design files are for a FIR (Finite Impulse Response) filter.
5
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Step 1 (Open ModelSim)
1. Start ModelSim from the Start Menu.
2. After you see the splash screen shown above, you should see the following window.
6
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Close this window and continue on to the next step.
Step 2 (Create a working library)
Note: Since all of the design files are in the project directory, reference libraries are
not required. Thus, you do not need to do any library mapping. You only need to
have a working library.
1. In the Main window of the ModelSim User Interface, go to the File Menu. Select
Change Directory and browse to the one of the following directories where you have
installed the labs:
<lab_install_dir>/lab1_2/Verilog or <lab_install_dir>/lab1_2/VHDL.
Note: The main window in Modelsim does not have the word “Main” in the title bar.
It has the phrase “Modelsim Altera 6.1d – custom Altera Version” This window will
be referred to as “Main” in the rest of the exercises.
2. Click OK
3. In the Main window of the ModelSim User Interface, choose the File menu. From
the File menu, click on New -> Library…. The dialog box below will appear.
4. In the Create box, make sure a new library and a logical mapping to it is selected.
Note: Again, library mapping is not required since there are no reference libraries
being used.
5. The Library Name field should already say work. If not, please type the word work
in the Library Name field. Also make sure that the Library Physical Name field
says work.
7
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
You must have a working directory to compile your design files into design units.
This step will create that library.
6. Click OK.
Notice that ModelSim has transcribed the commands to the Command Console as you
made selections in the User Interface. These commands could be copied to a .DO file
to automate these operations in the future.
Step 3 (Compile Design Files)
1. From the Compile menu of the Main window, select Compile….
The Compile HDL Source Files dialog box below opens.
2. Compile the design files:
For Verilog: Highlight each file in the Verilog directory and click on the Compile
button. You may also highlight all of the files and hit the Compile button once.
For VHDL: Highlight and click on the Compile button for each file in the VHDL
directory. Make sure that you compile all lower level files first (i.e. compile
filter.vhd last). This is necessary since filter.vhd is the top-level design file and its
8
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
architecture will reference the other design units in the directory. You may also
highlight all of the files except for filter.vhd and hit the Compile button, then
compile filter.vhd alone.
3. Click Done to close the Compile HDL Source Files dialog box.
With everything compiled, you can now select the design unit you want to simulate
and start the simulator.
Step 4 (Start the Simulator)
1. From the Simulate menu in the Main window, select Start Simulation....
The Simulate dialog box will now appear. In this box are listed all of the primary
suitable design units (entities, configurations, and modules) that can be simulated.
2. The Resolution box should read default. Click on this box to reveal a drop down
menu with various resolution times. Choose ns.
3. Expand the work library by clicking the plus sign to the left of it.
You can choose to simulate any design unit in any library being referenced by the
current design including design units in the built-in libraries.
4. Verilog: Highlight the filter module.
VHDL: Highlight the filter entity. Notice the plus sign next to filter. Click to
expand to show the architecture that is related to the entity filter. If there were
multiple architectures related to this entity, you could pick the one you wanted to
simulate at this point.
5. Click OK.
The Main window will now show that all of the entities / modules related to the
selected entity / module have been loaded.
The simulator is now ready to be advanced. In the next lab, you will advance the
simulator and view other ModelSim windows.
END OF EXERCISE 1
9
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
10
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Exercise 2
11
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
12
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Exercise 2
Objectives



To understand the purpose of the various ModelSim windows
To practice using the ModelSim windows interactively
To create a DO file containing force commands as simulator stimulus
13
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Please return to ModelSim. Step 1 below continues from where you left off in the
Lab Exercise 1.
Step 1 (The Source Window)
1. From the Workspace window, click on double click on u2, this will open then
Source Window.
2. Double Click on different design entities in the Workspace window in the main
window.
As you click on different design entities, the Source window updates dynamically to
show the source code that matches the selected region in the Workspace window.
Even VHDL packages can be viewed.
Also, notice in the Source window that the line numbers for all the lines of executable
code are in red, while the line numbers for non-executable code are in black.
3. Click on u3: state_m to view its code in the source window. Go to the Source
window and find line 38 (Verilog) or line 28 (VHDL). Click on the line number. A
small red ball will appear next to the line number. This indicates that a breakpoint
has been set. Make sure this is the only breakpoint set.
If you accidentally place a breakpoint on the wrong line, right-click on it and choose
Remove Breakpoint #.
14
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Step 2 (The Objects Window)
1. In the Main Window, go to the View menu and then to Debug Windows, and select
objects. On the command line, type view objects as shown below and then press
Enter.
This is another way to open a new ModelSim window. The Objects window will open
in the middle of the Main window to the right of the Workspace window.
2. Double Click on u2: hvalues in the Workspace and then double click on u1: taps.
Notice the Objects window, along with the Source window, changes according to the
region that is selected in the Workspace.
3. In the Objects window, go to the View menu and select Filter. In the Filter Menu,
un-check internal signals.
Now you only see I/O ports shown in the Signals window.
4. In the Workspace window, highlight the top-level region, filter: filter.
5. In the Objects window, go to the Add menu and then to Wave and click on Signals
in Region.
The Wave window opens with all of the I/Os and internal signals or wires listed.
15
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
6. In the Main Window, go to the View menu and then to Debug Windows, and select
List.
The List window should open on bottom right hand corner and will open with no
signals displayed.
7. From the workpace window, click on the top-level region, filter: filter, and drag it
over to the List window.
All of the I/Os and signals should now appear in the List window. This is to show
another way of adding signals to either the List or the Wave windows. Clicking and
dragging can also be done from the Signals window.
Step 3 (The Process window)
1. In the Main window, on the command line, type view process and press Enter.
The Process window opens underneath the object window. The Process window
shows all of the processes that are in the region highlighted in the Workspace
window regardless of their current execution state.
2. Close the object window, in the Main Window, go to the View menu and then to
Debug Windows, and select Object. Just like with the Object window, go to the
Workspace window and switch between u1, u2, and filter to change the processes
shown.
3. In the Workspace window, highlight u4.
Verilog: In the Process window, you will see one process being generated by an
assign statement. Select #ASSIGN#7.
VHDL: In the Process window, you will see one process being generated by a signal
assignment. Select line__13.
Notice the Source window now displays the code generating the process and a
pointer to indicate where the process will begin execution. Also notice that the
process name corresponds to the line number for the statement. This is because the
process was not given a label name. Also, by highlighting this process in the Process
window, you can force it to be the first process to be executed once simulation begins.
16
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Step 4 (The Dataflow Window)
1. In the Main Window, go to the View menu and then to Debug Windows, and select
Dataflow.
The Dataflow window opens at the bottom of the screen on the far left. You might see
a Warning that no extended dataflow license exists, since the OEM version of
ModelSim has limited Dataflow functionality. Click the warning to clear it from the
Dataflow window.
2. In the main project Workspace window, select the top level module (filter) again.
3. In the objects window, go to the View menu and Filter and turn Internal Signals
back on. Click on signal mult_to_acc and drag it to the Dataflow window.
4. Click on a signal on the left side of the process, /filter/u4/#ASSIGN#7 (Verilog) or
/filter/u4/line__13 (VHDL).
Notice that the Workspace, Objects, Active Process, and Source windows have all
interactively changed to indicate the process you have just selected.
We are now ready to simulate. First we must make a .DO file.
Step 5 (Making a .DO file)
1. In the Source window, go to the File menu and then New and click on Source, then
Do. This will open up a blank text editor sheet. Save this file as stimulus.do.
2. Using the class slides as a reference (see slide titled “force Command Examples”),
create a stimulus DO file that consists of force commands that will build the
simulation waveforms shown in the following figure:
Note: You will only need to force the inputs clk, reset, newt, and d.
Hint: This can be done with 4 lines. Here is one way to create the clk signal:
Eg...
force /clk 0 0 ns, 1 {10 ns} -r 20 ns
17
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
ie. (decimal 16)
3. Save file stimulus.do.
4. Close the file stimulus.do.
Step 6 (Run Simulation)
1. In the Main window, go to the Tools menu and select Execute Macro…. Choose the
file stimulus.do and click on the Open button.
Nothing happened! This is because you have scheduled events using the force
commands but you have not advanced simulation time.
2. In the Main window, go to the Simulate menu and select Runtime Options and
change the default Run to 100ns. Click OK.
3. In the Main window, go to the Simulate menu and select Run -> Run 100 ns.
In the Main window, go to View then Debug and then click on Wave.
This time the wave forms appear as simulation is being advanced. You may have to
zoom in or out a few times to see the transitions.
4. In the Main window, type run and press Enter.
The run command with no arguments advances 100 ns. This time, though, the
simulator came upon the breakpoint we set in u3: state_m. This pauses simulation
and the Source window shows a blue pointer to indicate where current execution
point is positioned. Notice its on line 38 (Verilog) or line 28 (VHDL) where the
breakpoint was set.
18
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
5. In the Main window, type run –continue and press Enter. (no space between the “-“
and continue.
This bypasses the breakpoint and finishes the 100 ns simulation run,
6. In the Main window, type step and press Enter. Repeat typing step a few more
times.
This will execute a single line of code, stepping into any subprogram that may be
called.
6. In the Main window, type run @300 ns.
This will advance the simulator to 300 ns. Since you did not clear the breakpoint, you
will have to do a run –continue when simulation pauses.
7. In the Main window, go to the Simulate menu and select Run -> Restart…. When
the Restart dialog box appears un-check Breakpoints. Click Restart.
This starts the simulation over at 0 simulation time, but saves all the window settings
while deleting the breakpoint, so you do not have to re-enter signals in windows.
8. Re-run the stimulus.do macro. Re-run the simulation for 400 ns.
Step 7 (The Wave Window)
1. In the Wave window, select signal /filter/d and then right-click. Click on Radix and
choose Decimal. Perform the same procedure on /filter/yn.
Do not worry about the initial state of the outputs. Verify from when they are
asserted.
19
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
2. Go to the Insert ( in Wave window) or Add (in Main window) menu and click on
Cursor. Do this twice. ( In the Main window )
The new cursors are displayed in the wave display area, each with their own tracks at
the bottom of the window. There is only one active cursor at any time, the other two
are shown as dotted lines. Simply click on a cursor to make it the active cursor.
Cursor measurement is always on to show the time distance between cursors.
3. Go to the View menu and click on Wave -> Zoom -> Zoom Range…. In the Wave
Zoom dialog box, type 0 ns as the Start and 400 ns as the End. Click Apply. Click
OK.
This sizes the Wave window for you. You can also zoom in and out manually.
Step 8 (The List Window)
In the Main window, go to the View menu, debug Windows and click on List. (If
your wave window was closed for some reason, it will be empty. Simply drag Filter
from the main window into the list window to restore the signals.
In the List window, each signal transition during simulation causes a new line in the
table to be displayed.
1. In the List window, go to time unit 90 ns.
Notice the +0, +2, +3, and +4 shown under 90 ns.
20
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
The List window displays the time values as well as the delta iterations in between
timesteps. Delta iterations are signal changes that occur at the same timestep, but
must be executed by the simulator one at a time. For example, a process causes
signal “a” to change at time 10. This would be considered delta +0. If another
process, containing signal “b” is sensitive to the transition of signal “a”, then it
would execute at delta +1. Thus, the transitions on both signals “a” and “b” occur
at timestep 10, but at different deltas during that timestep.
By default, deltas are expanded, thus each individual delta during each timestep is
displayed.
1. Go to the Tools menu and click on Window Preferences…. In the Trigger tab, in
the Deltas box, choose Collapse Deltas. Click Apply.
The List window will now only show the last delta for each time step. This means
that only the final state of all the listed signals during that timestep are displayed.
2. In the Trigger On box, un-check Signal Change and check Strobe. Set the Strobe
Period to 100 ns and the First Strobe at to 0 ns. Click Apply.
By default, any change in value of any listed signal triggers a line in the List window.
With Strobe turned on, the List window only displays the state of signals every strobe
period (100 ns).
3. In the Trigger On box, re-check Signal Change and un-check Strobe. Click Apply
and OK.
4. Go to timesteps 110 and 120.
Notice that between these two timesteps, clk is the only signal that is transitioning.
Since ANY signal transition causes a line to be printed in the List window, the clock
transition has caused line 120 to be printed even though nothing else is occurring
during that time period. What if your design had a very high-speed clock? You
would have hundreds of lines in the List window that were only clock transitions.
5. In the List window, select the clk signal. Go to the View menu and click on Signal
Properties…. In the Trigger box, select Does not trigger line. Click Apply.
Now, clk transitions do not cause a line to be printed in the List window. Notice that
timestep 120 is no longer displayed.
The Strobe command along with triggering allows you to control your List window so
as not to be overloaded with too many transitions.
21
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Step 9 (Using ModelSim to debug)
1. In the Wave window, study the waveforms for /filter/yvalid and /filter/nxt. Is there
a difference between your waveform and the waveform shown in the figure of Step 8?
2. Use the ModelSim skills you have learned to determine why these signals are
functioning differently. Repair the source code to correct for the design error. Ask
the instructor if you need any help.
Note: to edit HDL files in the cource window in ModelSim you must detach them from
the main ModelSim tool (right-click and undock); then go to the File menu and
un-check the read-only option so that you can write to them.
Step 10 (End Simulation)
1. In the Main window, go to the Simulate menu and select End Simulation.
2. Click on Yes.
Note: As a general rule, you probably don’t want to have all the ModelSim tool windows
open at one time when you are using the tool, so you may with to close some of
them before you proceed onto subsequent labs. This will give you more room to
work.
END OF EXERCISE 2
22
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Exercise 3
23
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
24
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Exercise 3
Objectives:




Gain understanding of the steps to perform a RTL (functional) simulation with
LPM functions and Altera MegaFunctions
Simulate Altera Memory Blocks
Practice mapping to a reference library
Practice ModelSim simulation using a test bench
Note: This lab exercise contains design files in both Verilog and VHDL. These
instructions are for both. Please choose the HDL language with which you are
more comfortable. The design files are for a FIR (Finite Impulse Response) filter.
25
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Section 1 (Use Altera Megafunctions and LPM Funcitons)
1. From the Windows Start Button menu, choose Run.
2. Type <QuartusII_install_dir>\bin\qmegawiz.exe (or just qmegawiz.exe).
This will open the Quartus II MegaWizard Plug-In Manager. Typically, the
MegaWizard is reached from the Quartus II User Interface, but you can also run the
MegaWizard independently if you do not need any of the other Quartus II software
functionality. This is especially useful if you are using another EDA tool or text
editor to enter the HDL design files and you quickly want to incorporate a
megafunction into your design.
3. On Page 1 of the MegaWizard Plug-In Manager, select Create a new custom
megafunction variation for the type of action to perform. Click on Next.
4. On Page 2a, under the Select a megafunction text, expand the arithmetic folder
and highlight LPM_MULT. For the type of output file to create, choose Verilog
HDL or VHDL accordingly. For the name of the output file, browse to and then
type either <lab_install_dir>\lab3\verilog\ lab_design_files\mult_lpm or
<lab_install_dir>\lab3\vhdl\lab_design_files\mult_lpm. For the type of device
family select Stratix II from the drop down menu. Click Next.
5. On Page 3, use the drop-down arrows to set
the How wide should the ‘dataa’ input bus be? 8 bits and
the How wide should the ‘datab’ input bus be? 3 bits.
6. Click Next until page 5.
7. On Page 5, Select “Yes, I want an output latency of 1 clock cycles” . Click
Next until page 7.
8. On Page 7, make sure that all the check boxes are checked. Click Finish.
9. From the Windows Start Button menu, choose Run.
10. Type <QuartusII_install_dir>\bin\qmegawiz.exe (or just qmegawiz.exe).
11. On Page 1 of the MegaWizard Plug-In Manager, select Create a new custom
megafunction variation for the type of action to perform. Click on Next.
12. On Page 2a, under the Select a megafunction text, expand the memory compiler
folder and highlight ROM: 1-PORT. For the type of output file to create, choose
Verilog HDL or VHDL accordingly. For the name of the output file, browse to
26
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
and then type either <lab_install_dir>\lab3\verilog\ lab_design_files\hvalues_mf
or <lab_install_dir>\lab3\vhdl\lab_design_files\hvalues_mf. For the type of
device family select Stratix II from the drop down menu. Click Next.
13. On page 3, Go to “How wide should the ‘q’ output bus be” field, select 3 bits.
14. Go to “How many 3-bit words of memory” field, select 4 words. Click Next.
15. On page 5, Go to “Do you want to specify the initial content of the memory?”
Field. Select “Yes, use this file for the memory content data”. Click Browse and
choose “hvalues_mf_init.hex” as the initialization file for the memory. Click
Next until page 7.
16. On page 7, make sure that all the checkboxes are checked. Click Finish.
Section 2 (Create a reference library)
17. Start ModelSim from the Start Menu.
18. After you see the splash screen, you should see the “IMPORTANT Information”
window. Close this window and continue on to the next step.
19. In the Main window of the ModelSim User Interface, go to the File Menu.
Select Change Directory and browse to the one of the following directories where
you have installed the labs:
<lab_install_dir>/ Lab3/verilog/lab_library or
<lab_install_dir>/ Lab3/vhdl/lab_library.
20. Click OK.
21. In the Main window of the ModelSim User Interface, choose the File menu.
From the File menu, click on New -> Library…. The dialog box will appear.
22. Type my_arithmetic_library in the “Library Name” field. Click OK.
23. In the Main Window, go to Compile menu and select Compile. This will bring up
“Compile Source Files” window.
24. Select my_arithmetic_library in the “Library” field.
25. Highlight acc.vhd/v and click on Compile. Click on Done.
27
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
26. In the Main window of the ModelSim User Interface, go to the File Menu.
Select Change Directory and browse to the one of the following directories where
you have installed the labs:
<lab_install_dir>/ Lab3/verilog/lab_design_files or
<lab_install_dir>/ Lab3/vhdl/lab_design_files.
Section 3 ( Create a Project )
27. Under File, Select New then select Project. This will bring up page “Create
Project”.
28. Type my_project in the Project Name field.
29. Select the directory in the Project Location field. ( Project location Field should
show “lab_design_files” directory. If not, click on cancel and go back to step 26 )
30. Leave the name “work” under “Default Library Name” field.
31. Click OK. This will bring up page “Add items to the Project”.
Step 3 ( Add items to the Project )
32. Click “Add Existing File”
33. This will bring up “Add file to Project”. Click “Browse”.
34. Select the following files : ( press and hold “Ctrl” key and select the following
files) filter.vht, filter.vhd/v , hvalues_mf.vhd/v,mult_lpm.vhd/v,
state_m.vhd/v, taps.vhd/v.
Click Open in the Select files to add to project.
35. Click OK at the Add File to Project window.
36. Click Close at the Add items to the Project window.
Section 4 ( For VHDL users – go to the next step - Compile Order.
For Verilog users, go to the next section - Compilation )
37. Go to Compile menu item, then select Compile Order.
38. Click on Auto Generate button.
39. Click OK at the Compile Order window.
28
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Section 5 ( Logical mapping to reference library.)
40. In order to create a logical mapping to my_arithmetic_library ( it is created in
the “ Create a reference library” section ), go to file menu in the main window.
Select new->library. This will bring up “Create a New Library”.
41. Select “a map to an existing library” option in the Create field.
42. Type my_arithmetic_library in the library name field.
43. In the “Library maps to” field, click Browse select
…/lab_library/my_arithmetic_library. Click OK.
Section 6 ( Compilation )
44. Go to Compile menu item, then select Compile All.
45. Go to Workspace then select Library tab. Click on the “+” sign next to the work
library.
46. You should be able to see compiled design units at Library tab.
47. Go to Simulate menu item, select Start Simulation.
48. Click on the “+” sign next to the work library.
49. Highlight filter_vhd_vec_tst ( or corresponding Verilog File). Select “ns” for
Resolution.
50. Click OK at the Start Simulation window.
51. You will see new tabs under Workspace: Sim, Files, Memories
52. In order to see the structure of the Filter design, click on Sim Tab.
53. In order to see detailed information about the source files, click on Files Tab.
Go back to Project Tab in the Workspace section of the main window.
Section 7 (Organize your design files)
54. Right-Click anywhere in the Workspace-> Project Tab. Select Add to Project->
Folder. Type filtertaps in the Folder Name field. Click OK.
55. Right-Click on “taps.vhd/v” then select Properties. Go to Place in Folder field.
Select “filtertaps”. Click OK.
56. Repeat steps 54 and 55 for the following files:
29
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
File Name
Folder Name
mult_lpm.vhd/v
multiplication
state_m.vhd/v
statemachine
hvalues_mf.vhd/v
coefficients
57. In the Workspace section of the main window, click on the “+” sign next to
statemachine, filtertaps, multiplication and coefficients folders. You will “?” at the
status column for the files you just put in the folders. ModelSim-Altera doesn’t
know anything about the status of these files. You need to recompile the design
files.
58. Go to Compile menu and select “Compile All”.
Section 8 ( Simulation )
59. Go to “Simulate” menu in the main window. Select “Start Simulation”.
60. Click on “+” sign next to the work library. Select filter_vhd_vec_tst. ( or
corresponding Verilog Fil) Go to Resolution field and select “ns”. Click on OK.
Section 9 ( Add Simulation Configuration )
61. In the previous step, you selected simulation options. Every time you start to
simulate, you need to select these options. With Simulation Configuration file, you
will specify these options for the design once.
62. Quit simulation. Go to Simulation menu, and select “End Simulation”.
Go back to Project Tab.
63. Go to File menu. Select “Add to Project”-> “Simulation Configuration”. This
will bring up “Add Simulation Configuration” window.
64. In the “Add Simulation Configuration” window, Go to “Simulation
Configuration Name” field, type my_configuration.
65. Click on the “+” sign. Select “filter_vhd_vec_tst”.
66. Go to Resolution field, select “ns”. Click OK.
30
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Section 10 ( Simulation )
67. Go to Compile menu and select “Compile All”.
68. Go to “Simulate” menu in the main window. Select “Start Simulation”.
69. Click on the “+” sign next to the work library. Select “filter_vhd_vec_tst”. Click
OK.
70. Include following signals into the wave window: clk, reset, newt, d, yvalid, nxt,
yn.
71. In the command line, type “run 400 ns”.
Step 11 (End Simulation)
72. In the Main window, go to the Simulate menu and select End Simulation….
73. Close ModelSim.
END OF EXERCISE 3
31
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
32
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Exercise 4
33
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
34
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Exercise 4:
Lab Summary:
In this exercise we will be performing a timing-based simulation on a netlist
synthesized from the RTL code we used in Exercises 1 to 3. The .vqm netlist is
provided for you in the lab folder. It was synthesized in Synplify Pro instead of
Quartus II, so in this lab we are adding another dimension to the lab – ie. working
with output from a 3rd party synthesis tool.
Learning Objectives:




Incorporate a 3rd party synthesized netlist into Quartus II
Produce output timing simulation files from Quartus II
Perform a timing simulation in ModelSim with output files from Quartus II
Map to pre-compiled libraries in ModelSim
35
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Step 1 (Open Project Files in Quartus II & Pick Device)
1. Open Quartus II from the Start menu.
2. From the File menu, select Open Project and browse to the directory
<lab_install_dir>\lab4.
3. Select lab4.qpf and click Open.
Note: A Quartus II project has already been created for you. You are going to use
the pre-existing project to generate the proper files to perform timing simulation.
Step 2 (Set Quartus II Input File Type)
1. Go to the Assignments menu and select EDA Tool Settings….
2. In the Design Entry & Synthesis field, use the drop-down menu under Tool name to
select Synplify Pro. Also, ensure that the file format is set to VQM.
Step 3 (Set Quartus II to Generate Output Simulation File)
1. Under EDA Tool Settings select Simulation
2. In the Simulation field, use the drop-down menu under Tool name to select either
ModelSim-Altera (Verilog HDL )or ModelSim-Altera (VHDL), depending on
which language you would like to use in ModelSim.
3. Make sure that Run this tool automatically after compilation is unchecked.
4. Click OK.
Step 4 (Compile in Quartus II)
1. Go to the Processing menu and click on Start Compilation.
When compilation is finished, Quartus II will have produced the necessary output
files required for you to perform timing simulation in ModelSim. You will continue
to use the same project directory as you did in Quartus II to simulate in ModelSim.
Observe that there is now a “simulation/modelsim” directory inside your project
directory.
Step 5 (In ModelSim Change to Simulation Directory)
36
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
1. In the Main window of ModelSim, go to the File menu and select Change
Directory.
2. Browse to the directory <lab_install_dir>/lab4/simulation/modelsim/. (This subdirectory gets created if you specify ModelSim as the EDA simulation tool in Quartus
II prior to compiling.)
3. Click OK.
Step 6 (Compile Design Files in ModelSim)
1. In the File menu, select New -> Library…. Choose a new library and a logical
mapping to it. Type work in the Library field if it is not already there. Click OK
2. In the Compile menu, click Compile….
3. In the Library field, choose work.
4. Select the file lab4.vo (Verilog) or lab4.vho (VHDL) and click Compile.
Change the Files of type: setting to All Files (*.*) to see the Verilog output file.
5. Click Done.
Step 7 (Start the Simulator)
1. In the Simulate menu, select Start Simulation….
2. In the Start Simulation dialog box, click on the SDF tab and click Add.
3. In the Add SDF Entry dialog box, click Browse.
4. Browse to the simulation/modelsim directory in the Files of type list, and select All
Files(*.*).
5. Select the file lab4_v.sdo (Verilog) or lab4_vhd.sdo (VHDL). Click Open. Click
OK.
6. For Verilog Only we now need to add the specific family library: In the Simulate
dialog box, click on the Libraries tab. In the Search Libraries field, click Add.
Browse to the directory <modelsim_install_dir>\altera\verilog\stratix\ then click
OK.
37
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
This will cause ModelSim to search the necessary libraries when looking for design
units. VHDL output files from Quartus II can have pre-written library declarations,
but the Verilog HDL does not have library referencing.
7. In the Simulate dialog box, click on the Design tab.
8. Select ps for the Simulation Resolution.
9. Expand the work library.
10. Highlight the filter entity or module.
11. Click OK.
Step 8 (Setup ModelSim Windows)
1. If you have closed the other ModelSim windows from the previous lab exercise, in
the Main window, type view wave.
2. Next, in the Main window, type add wave /*.
Step 9 (Run Do File)
Verify timing delays are included in the simulation by executing the supplied DO file.
1. In the Tools menu of the Main window, select the Execute Macro… option.
2. Locate the file stimulus.do (in the <lab_install_dir>\lab4 directory) and click Open.
Step 10 (Advance the Simulator)
1. Type run @400 ns. (Be sure to zoom out in the Wave window to see the entire
simulation wave form.)
Notice in this simulation that other signal transitions do not occur immediately at
clock edges. This is due to ModelSim incorporating device timing delays provided by
the SDF file. What is the clock to output time in nanoseconds for yn?
38
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Step 11 (End Simulation)
74. In the Main window, go to the Simulate menu and select End Simulation….
75. Close ModelSim.
END OF EXERCISE 4
39
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
40
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Exercise 5
41
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
42
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
Exercise 5:
Objectives
To learn to
Create a custom variation of the DDR2 SDRAM Controller MegaCore
function using the Altera DDR2 SDRAM Controller IP Toolbench and the Quartus II
Software.
Simulate the example design generated with IP-Toolbench with ModelSim
Simulator.
43
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Section 1- Create a New Quartus II Project
1. Choose Programs > Altera > Quartus II <version> (Windows Start
menu) to run the Quartus II software.
2. Choose New Project Wizard (File menu).
3. Click Next in the introduction
4. Specify the working directory for your project. (<installation directory>\lab5 )
5. Specify the name of the project as example_top.
----- You must specify the same name for the project name and the
top-level design entity name.
6. Click Next in page 1.
7. Click Next in page 2.
8. Choose the target device family in the Family list: (Stratix II - EP2S60F1020C3 )
9. Click next. Check the EDA Simulation Check box. Select ModelSim-Altera (VHDL
or Verilog). Click Finish.
10. You have finished creating your new Quartus II project.
Section 2- Launch IP Toolbench from the MegaWizard Plug-In Manager
To launch the wizard in the Quartus II software, follow these steps:
Start the MegaWizard® Plug-In Manager by choosing the
MegaWizard Plug-In Manager command (Tools menu). The
MegaWizard Plug-In Manager dialog box is displayed.
1. Specify that you want to create a new custom megafunction
variation and click Next.
2. Choose DDR2 SDRAM Controller v3.3.1 in the Interfaces > Memory Controllers
directory.
3. Choose the output file type for your design; the wizard supports
VHDL or Verilog HDL only.
4. Specify a name for the output file : …….\ddr2_megacore
44
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
6. Click Next to launch IP Toolbench.
Section 2.1- Parameterize
To parameterize your MegaCore function, follow these steps:
1. Click Step 1: Parameterize in IP Toolbench
2. In the Presets list, choose a specific memory device Micron MT47H16m16bg-5E
3. Enter 200 MHz in the Clock Speed field.
4. You can go through the parameter tabs with the instructor. Our objective in this lab is
to show you the simulation flow. Because of this reason, leave the parameters in their
default value.
5.. Click Finish.
Section 2.2- Constraints
To choose the constraints for your device, follow these steps:
1. Click Step 2: Constraints in IP Toolbench
2. Choose the positions on the device for each of the DDR SDRAM
byte groups To place a byte group, select the byte group in the dropdown
box at your chosen position.
The floorplan matches the orientation of the Quartus II floorplanner. The layout
represents the die as viewed from above. A byte group consists of eight DQ pins, a DM
pin, and a DQS pin.
IP Toolbench chooses the correct positions, if you are using an Altera board preset.
3. Click OK.
Section 2.3- Set Up Simulation
1. Click Step 3: Set Up Simulation
1. Turn on Generate Simulation Model
3.
Choose the language in the Language list.
45
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
4. Click OK.
Section 2.4- Generate
To generate your MegaCore function, follow these steps:
1. Click Step 4: Generate in IP Toolbench
2. The generation report lists the design files that IP Toolbench creates.
3. Click Exit.
Section 3- Simulate the Example Design
You can simulate the example design with the IP Toolbench-generated IP
functional simulation models. IP Toolbench generates a VHDL or Verilog
HDL testbench for your example design, which is in the testbench
directory in your project directory.
Simulating With the ModelSim Simulator
To simulate the example design with the ModelSim® simulator, follow
these steps:
1. Obtain a memory model that matches your chosen parameters and
save it to the <directory name>\testbench directory. For example,
you can download a Micron memory model from the Micron web
site at www.micron.com. Please copy the following files from the <installation
directory>\lab_5\memory_models directory to your <directory name>\testbench
directory:
ddr2.v
ddr2_parameters.vh
2. For VHDL, edit generic_ddr_sdram.vhd to instantiate your
memory model (the file already contains three example Micron
memory model instantiations).
Or
For Verilog HDL, edit the memory instantiations in the testbench to
match your memory model.
Ref: Slide 158 from Class Presentation
46
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
3. Start the ModelSim-Altera simulator.
4. Change your working directory to your IP Toolbench-generated file
directory <directory name>lab_5\testbench\modelsim.
5. Type the following command:
set memory_model <model_name>
set memory_model ddr2
where <model_name> is the filename of the downloaded memory
model.
6. To simulate with an IP functional simulation model simulation, type
the following command:
source ddr2_megacore_ddr_sdram_vsim.tcl
7. For a gate-level timing simulation (VHDL or Verilog HDL
ModelSim output from the Quartus II software), type the following
commands:
set use_gate_model 1
source ddr2_megacore_ddr_sdram_vsim.tcl
8. In ModelSim Wave Window, Go to the DDR SDRAM IF (interface)section.
DDR SDRAM Interface
Local Interface
47
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Exercises
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
48
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01
Analyzing Designs Using the Mentor Graphics ModelSim-Altera Simulation Tool
Exercises
8. The table below shows the standard SDRAM bus commands. Do you see the same
relationship in wave window between ras_n,cas_n,we_n and command lines?
Command
Acronym
ras_n
cas_n
we_n
No operation
NOP
HIGH
HIGH
HIGH
Active
Read
Write
Burst Terminate
Precharge
Auto refresh
Load mode register
ACT
RD
WR
BT
PCH
ARF
LMR
LOW
HIGH
HIGH
HIGH
LOW
LOW
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
LOW
9. DDR2 SDRAM controller must open SDRAM banks before they access address in
that bank. The row and bank to be opened are registered at the same time as the active
(ACT) command. Go to 203085 ns in the wave window in order to see the
relationship between Read (RD) and Active(ACT) commands.
10. In order to access a different row, DDR2 Controller close the bank and open it again.
The “Precharge” (PCH) command closes a bank. Go to 203070 ns in the wave
window in order to see the relationship among PCH, ACT and RD commands.
11. Check the relationship between DQ and DQS signals. Do you see any difference in
this relationship during RD and WR commands?
(End Simulation)
12. In the Main window, go to the Simulate menu and select End Simulation….
13. Close ModelSim
49
Copyright © 2005 Altera Corporation
A-MNL-MS-ALTR-EX-01