EE 5900 Advanced
Algorithms for Robust
VLSI CAD, Spring 2009
Static Timing Analysis and Gate
Sizing
Delay Evaluation


1. Gate delay
2. Interconnect delay
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Circuit Delay
PJF- 2
1. Problem Description

Given a pair of pins, compute pin-to-pin
delay and possibly output waveform
Delay
Cell
Interconnect
Cell
…
Cell
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Circuit Delay
PJF- 3
Circuit Model

For an inverter
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Circuit Delay
…
Csink
…
Csink
PJF- 4
Sink Capacitance



Gate capacitance, input
capacitance
Given for standard cells
Can be found using SPICE
Apply an AC voltage and
measure current
 Average over a range of
frequency

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Circuit Delay
I
PJF- 5
Capacitance Model
RC
Rd
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Rd
Circuit Delay
Ctotal
PJF- 6
Interconnect Delay: Elmore
Delay


Elmore is used as the delay on
interconnect
Easy to compute
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Circuit Delay
PJF- 7
Example
1
1
1
1
2
1
1
3
1
4
1
1
m1_1= –4, m1_2= –7, m1_3= –8, m1_4= –8
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Circuit Delay
PJF- 8
Application of Elmore Delay

Good
Closed form expression, easy to compute
 Useful in circuit design such as gate sizing
and buffering.


Bad
Inaccurate
 Not useful for timing verification

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Circuit Delay
PJF- 9
Circuit Delay Evaluation - Two
Components

Cell delay + interconnect delay
Cell delay is computed using RC or Kfactor
 Interconnect delay is computed using
Elmore delay

Cell
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Interconnect
Circuit Delay
Cell
PJF- 10
Static vs. Dynamic Timing Analysis

Static timing analysis



Fast
Consider all paths
Pessimism by considering
false paths which are
never exercised

Dynamic timing analysis
( simulation )



Depends on input stimulus
vectors
Do not report timing on
false paths
With large number of
testing vectors


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Circuit Delay
Accurate
Slow
PJF- 11
Wire and Gate Models
l
B
h
r0 l
h
c( h )l
2
rB
c( h )l
2
CB
12
Step by Step




Model combinational circuit using the previous
slide
Starting from primary input gates, compute
the arrival time (AT) at each gate, i.e.,
compute gate delay and interconnect delay
In order to compute the AT at a gate, the
ATs of all its input gates need to be computed
Repeat the above process until the ATs at all
primary output gates are computed
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Circuit Delay
PJF- 13
Example of Static Timing Analysis
C=1,R=1
C=5,R=2
10
1
AT=0
AT=121
C=4,R=2
C=10,R=5
5
3
AT=22
2
AT=167
AT=31
C=5,R=2
AT=145
2
AT=21
2
AT=0
4
AT=75
12
AT=267
2
AT=12
AT=31
Take the
Max
AT=267
unit wire resistance=1
unit wire capacitance=1

Arrival time (AT): input -> output, take max
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Circuit Delay
PJF- 14
Timing Optimization
C=1,R=1
C=5,R=2
10
AT=121
AT=0
AT=145
2
AT=21
C=4,R=2
2
AT=167
AT=31
C=5,R=2
AT=22
AT=75
12
C=10,R=5
Should we
size up this
gate to
improve
timing?
AT=267
2
AT=0
AT=12
AT=31
Take the
Max
AT=267
unit wire resistance=1
unit wire capacitance=1

Arrival time (AT): input -> output, take max
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Circuit Delay
PJF- 15
Timing Optimization- II


Suppose that we have a gate (with same
gate type) doubling its width. We roughly
have C=10, R=1.
If we change the gate with this new one,
what is the new delay? Does not change
C=1,R=1
C=5,R=2
10
AT=121
AT=0
AT=145
2
AT=21
C=4,R=2
2
AT=167
AT=31
C=10,R=1
AT=16
AT=75
12
C=10,R=5
AT=267
2
AT=0
AT=6
AT=31
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Take the
Max
unit wire resistance=1
unit wire capacitance=1
AT=267
Circuit Delay
PJF- 16
Timing Optimization- III


Suppose that we have a gate (with same
gate type) doubling its width. We roughly
have C=8, R=1.
If we change the gate with this new one,
what is the new delay?
C=1,R=1
C=5,R=2
10
AT=125
AT=0
AT=149
2
AT=25
C=8,R=1
2
AT=171
AT=43
C=5,R=2
AT=38
AT=65
12
C=10,R=5
AT=257
2
AT=0
AT=20
AT=43
Take the
Max
unit wire resistance=1
unit wire capacitance=1
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AT=257
Circuit Delay
PJF- 17
Timing Optimization- IV



This optimization is called gate sizing.
Change the gate size (width) in
optimization.
1. Given multiple choices (implementations)
per gate type, find a gate implementation
at each gate such that the circuit timing is
minimized.
2. Given multiple choices per gate type,
find a gate implementation at each gate
such that the circuit timing satisfies the
target and the total gate area/power is
minimized
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Circuit Delay
PJF- 18
Problem Definition of Gate
Sizing


Given a timing (delay) target, use
smallest power/area gates to meet the
timing target
In general, smaller power -> larger
timing, smaller timing -> larger power.
19
Delay due to Gate Sizing

Suppose that unit width gate capacitance is c
and unit width gate resistance is r. Given gate
size wi,


Gate size wi: R  r/wi, C  cwi
Delay is a function of RC

Delay   RiCj   wi/wj
20
Wire and Gate Models
l
B
h
r0 l
h
c( h )l
2
rB
c( h )l
2
CB
21
Combinatorial Circuit Model


Gate size variables x1, x2, x3
Delay on each gate depends on x
a1
Drivers
D1
x1
a3
D4
a6
D6
D7
a2 D2
a4
D3 D5
D8
x2
22
D9
x3
a5 a7
D10
Loads
Path Delay




Express path delay in
terms of component
delay
A component can be a
gate or a wire
Delay D for each
component
Arrival time a for some
components
23
a1  D1  D4  a3
a2  D2  D4  a3
a2  D3  D5  a4
a3  D6  a6
a3  D7  D9  a5
a4  D8  D9  a5
a5  D10  a7
Gate Sizing

Power/area minimization under delay constraints:
Minimize

n
i 1
 i xi
Subject to a j  Amax j  primary output, Amax is the timing target
a j  Di  ai i and j  input (i )
Li  xi  U i i smallest and largest size on each gate

This can be solved efficiently using gpsolve
24
Gate Sizing using GPSOLVE

Follow the steps in gatesizing.m
25