Based on slides/material by…
‹
J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html
“Digital Integrated Circuits: A Design Perspective”, Prentice Hall
‹
D. Harris http://www.cmosvlsi.com/coursematerials.html
Weste and Harris, “CMOS VLSI Design: A Circuits and Systems
Perspective”, Addison Wesley
Topic 2
Basic MOS Theory, SPICE Simulation,
CMOS Fabrication
Peter Y K Cheung
Department of Electrical & Electronic Engineering
Imperial College London
URL: http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/
E-mail: [email protected]
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 1
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Recommended Reading
‹
J. Rabaey et. al. “Digital Integrated Circuits: A Design Perspective”:
Chapter 2 (2.1 – 2.3), Chapter 3 (3.3)
‹
Weste and Harris, “CMOS VLSI Design: A Circuits and Systems
Perspective”: Chapter 2, Chapter 3 (3.2), Chapter 5.
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 2
Outline
Topic 2 - 3
‹
MOS transistors
‹
SPICE simulation
‹
CMOS fabrication process
‹
Layout rules
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 4
Conduction Characteristics of MOS Transistors
(for fixed Vds)
MOS Transistor
‹
‹
‹
Shown here is the cross-section of an n-channel enhancement transistor:
Substrate is moderately doped with p-type material. Substrate in digital
circuit is usually connected to VGnd (ground).
The source and drain regions are heavily doped with n-type material
through diffusion. These are often referred to as the diffusion regions.
‹
‹
‹
‹
‹
‹
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 5
MOS transistors are majority-carrier devices.
For n-channel transistors, the majority carriers are electrons conducted
through a channel.
A positive gate voltage (w.r.t. substrate) enhances the number of
carriers in the channel, and increases conduction.
Threshold voltage Vtn denotes the gate-to-source voltage above which
conduction occurs.
For enhancement mode devices, Vtn is positive; for depletion mode
devices, Vtn is negative.
p-channel devices are similar to n-channel devices, except that all
voltages and currents are in opposite polarity.
MOS Theory, SPICE, Fabrication
Cross-Section of CMOS Technology
Introduction to Digital Integrated Circuit Design
MOS transistors - Types and Symbols
D
D
NMOS Enhancement
G
S
D
D
PMOS Enhancement
G
S
Introduction to Digital Integrated Circuit Design
Topic 2 - 7
NMOS Depletion
G
S
MOS Theory, SPICE, Fabrication
Topic 2 - 6
MOS Theory, SPICE, Fabrication
B
G
NMOS with
Bulk Contact
S
Introduction to Digital Integrated Circuit Design
Topic 2 - 8
Threshold Voltage: Concept
‹
+
S
V GS
-
MOS transistor (1)
D
G
‹
n+
n+
‹
‹
n-channel
Depletion
Region
p-substrate
‹
Between the diffusion regions is the gate area form from a layer of polycrystaline
silicon (known as polysilicon). This is separated from the substrate by a layer of
thin oxide (made of silicon dioxide). Polysilicon is reasonable conductor and
form the gate electrode.
Underneath the thin oxide and between the n+ regions is the channel. The
channel is conducting when a suitable electric field is applied to the gate.
Due to geometric symmetry, there are no distinctions between the source and
drain regions. However, we usually refer the terminal with more positive voltage
the drain (for n-type) and less positive voltage the source.
For a zero gate bias and a positive VDS, no current flows between the drain and
source because of the two reverse biased diodes shown in the diagram. The
drain and source are therefore isolated from each other.
Assuming that the substrate is always at the most negative supply voltage, these
two diode should never become forward bias under normal operation.
B
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 9
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
MOS transistor (2)
‹
‹
‹
‹
‹
The Threshold Voltage
When a positive voltage is applied to the gate, an electric field is produced
across the substrate which attracts electrons toward the gate. Eventually, the
area under the gate changes from p-type to n-type, providing a conduction path
between the source and drain.
The gate-source voltage VGS when a channel starts to form under that gate is
called the threshold voltage VT.
The surface underneath the gate under this condition is said to be inverted. The
surface is known as the inversion layer.
As larger bias is applied to the gate the inversion layer becomes thicker
An other p-n junction exists between the inversion layer and the substrate. This
diode junction is field induced. Contrast this with the p-n junction between the
source (or drain) and the substrate, which is created by a metallurgical process.
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 10
Topic 2 - 11
0
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 12
Current-Voltage Relations
V GS
S
V DS
G
n+
–
V(x)
Current-Voltage Relations
ID
D
n+
+
L
x
p-substrate
B
MOS transistor and its bias conditions
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 13
MOS Theory, SPICE, Fabrication
‹
VG S
‹
V DS > VGS - V T
‹
D
S
n+
MOS Theory, SPICE, Fabrication
-
VG S - VT
+
Introduction to Digital Integrated Circuit Design
Topic 2 - 14
MOS transistor (3)
Transistor in Saturation
G
Introduction to Digital Integrated Circuit Design
As a voltage is applied between the source and drain, the inversion layer
becomes thinner at the drain terminal due to interaction between VG and VD.
If VDS < VGS - VT, then the drain current Id is a function of both VGS and VDS.
Furthermore, for a given VDS, ID increases linearly with (VGS - VT). The transistor
is said to be operating in its linear or resistive region.
If VDS > VGS - VT, then VGS < VT and no inversion layer can exist at the drain
terminal. The channel is said to be 'pinched-off'. The transistor is operating in
the saturation region, where the drain current is dependent on VGS and is almost
independent of VDS.
n+
Topic 2 - 15
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 16
I-V Relation
MOS Theory, SPICE, Fabrication
A model for manual analysis
Introduction to Digital Integrated Circuit Design
Topic 2 - 17
MOS Theory, SPICE, Fabrication
Dynamic Behavior of MOS Transistor
Introduction to Digital Integrated Circuit Design
Topic 2 - 18
The Gate Capacitance
G
CGS
CGD
D
S
CGB
CSB
CDB
B
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 19
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 20
Average Gate Capacitance
Issues concerning Sub-Micron MOS Transistors
Different distributions of gate capacitance for varying
operating conditions
‹
‹
Threshold Variations
‹
Parasitic Resistances
‹
Velocity Saturation
‹
Mobility Degradation
Most important regions in digital design: saturation and cut-off
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 21
MOS Theory, SPICE, Fabrication
Threshold Variations
Introduction to Digital Integrated Circuit Design
Topic 2 - 22
Parasitic Resistances
VT
Long-channel threshold
Low VDS threshold
L
Threshold as a function of
the length (for low VDS)
MOS Theory, SPICE, Fabrication
Drain-induced barrier lowering
(for low L)
Introduction to Digital Integrated Circuit Design
Topic 2 - 23
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 24
Velocity Saturation (1)
Velocity Saturation (2)
1.5
0.5
I D (mA)
VGS = 3
0.5
VGS = 2
VGS = 1
0.0
1.0
2.0
3.0
4.0
5.0
ID (mA)
VGS = 4
1.0
Linea r Dependence
VGS = 5
0
0.0
VDS (V)
(a) I D as a function of V DS
1.0
2.0
V G S (V)
3.0
(b) ID as a function of V G S
(for VDS = 5 V).
Linear Dependence on VGS
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 25
MOS Theory, SPICE, Fabrication
Sub-Threshold Conduction
‹
‹
Linear region
‹
ln(ID) (A)
Topic 2 - 26
Latch-up problem (1)
10−2
10−4
Introduction to Digital Integrated Circuit Design
10−6
The p+ region of the p-transistor, the n-well and the p- substrate form a
parasitic pnp transistor T1.
The n- well, the p- substrate and the p+ source of the n-transistor forms
another parasitic npn transistor T2.
There exists two resistors Rw and Rs due to the resistive drop in the well
area and the substrate area.
10−8
10−10
10−120.0
MOS Theory, SPICE, Fabrication
Subthreshold exponential region
VT 1.0
2.0
3.0
VGS (V)
Introduction to Digital Integrated Circuit Design
Topic 2 - 27
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 28
Latch-up problem (2)
‹
‹
‹
‹
‹
Outline
T1 and T2 form a thyristor circuit.
If Rw and/or Rs are not 0, and for some
reason (power-up, current spike etc), T1
or T2 are forced to conduct, Vdd will be
shorted to Gnd through the small
resistances and the transistors.
Once the circuit is 'fired', both transistors
will remain conducting due to the voltage
drop across Rw and Rs. The only way to
get out of this mode is to turn the power
off.
This condition is known as latch-up.
To avoid latch-up, substrate-taps (tied to
Gnd) and well-taps (tied to Vdd) are
inserted as frequently as possible. This
has the effect of shorting out Rw and Rs.
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 29
‹
MOS transistors
‹
SPICE simulation
‹
CMOS fabrication process
‹
Layout rules
MOS Theory, SPICE, Fabrication
What is SPICE Circuit Simulator?
‹
‹
SPICE is a widely-used circuit-level simulator, originally from Berkeley.
SPICE uses numerical techniques to solve nodal analysis of circuit. It
supports the following:
‹
Resistors, Capacitors, Inductors
Independent sources (V, I), Dependent sources (V, I)
Transmission lines
Active devices (diodes, BJTs, JFETS, MOSFETS)
Level 3: Semi-Emperical - Based on curve fitting
to measured devices
You can use SPICE to perform the following types circuit analysis:
•
•
•
•
Level 4 (BSIM): Em perical - Simple and Popular
non-linear d.c.
non-linear transient
linear a.c.
Noise & temperature
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes Velocity
Saturation and Threshold Variations
You can use SPICE to specify these circuit components:
•
•
•
•
Topic 2 - 30
SPICE MODELS
• Textual input to specify circuit & simulation commands
• Text or graphical output format for simulation results
‹
Introduction to Digital Integrated Circuit Design
Topic 2 - 31
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 32
MAIN MOS SPICE PARAMETERS
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
SPICE Parameters for Parasitics
Topic 2 - 33
SPICE Transistors Parameters
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 34
Fitting level-1 model for manual analysis
Region of
matching
ID
Short-channel
I-V curve
V GS = 5 V
Long-channel
approximation
V DS = 5 V
V DS
Select k ’ and λ such that best matching is obtained @ V gs = V ds = V DD
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 35
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 36
Technology Evolution
‹
Outline
VDD decreases
• Save dynamic power
• Protect thin gate oxides and short channels
• No point in high value because of velocity sat.
‹
‹
‹
Vt must decrease to
maintain device performance
But this causes exponential
increase in OFF leakage
Major future challenge
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 37
‹
MOS transistors
‹
SPICE simulation
‹
CMOS fabrication process
‹
Layout rules
MOS Theory, SPICE, Fabrication
CMOS Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 38
Inverter Cross-section
‹
CMOS transistors are fabricated on silicon wafer
‹
Typically use p-type substrate for nMOS transistors
‹
Lithography process similar to printing press
‹
Requires n-well for body of pMOS transistors
VDD
Qp
Vo
Vi
Qn
‹
On each step, different materials are deposited or etched
‹
Easiest to understand by viewing both top and cross-section of wafer in
a simplified manufacturing process
A
GND
VDD
Y
n+ diffusion
n+
n+
p+
p+
n well
p substrate
nMOS transistor
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 39
SiO2
MOS Theory, SPICE, Fabrication
p+ diffusion
polysilicon
metal1
pMOS transistor
Introduction to Digital Integrated Circuit Design
Topic 2 - 40
Well and Substrate Taps
‹
Inverter Mask Set
Substrate must be tied to GND and n-well to VDD
‹
‹
‹
Metal to lightly-doped semiconductor forms poor connection called
Shottky Diode
‹
Use heavily doped well and substrate contacts / taps
Transistors and wires are defined by masks
Cross-section taken along dashed line
A
A
GND
VDD
Y
p+
n+
n+
p+
p+
Y
n+
n well
p substrate
GND
VDD
nMOS transistor
substrate tap
MOS Theory, SPICE, Fabrication
well tap
Introduction to Digital Integrated Circuit Design
Topic 2 - 41
‹
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Introduction to Digital Integrated Circuit Design
Topic 2 - 42
Fabrication Steps
Six masks
•
•
•
•
•
•
well tap
MOS Theory, SPICE, Fabrication
Detailed Mask Views
‹
pMOS transistor
substrate tap
‹
n well
‹
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
•
•
•
•
Polysilicon
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
n+ Diffusion
p+ Diffusion
Contact
p substrate
Metal
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 43
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 44
Oxidation
‹
Photoresist
Grow SiO2 on top of Si wafer
‹
• 900 – 1200 C with H2O or O2 in oxidation furnace
Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light
Photoresist
SiO2
SiO2
p substrate
MOS Theory, SPICE, Fabrication
p substrate
Introduction to Digital Integrated Circuit Design
Topic 2 - 45
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Lithography
‹
‹
Topic 2 - 46
Etch
Expose photoresist through n-well mask
Strip off exposed photoresist
‹
Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone; nasty stuff!!!
‹
Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
Photoresist
SiO2
p substrate
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 47
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 48
Strip Photoresist
‹
n-well
Strip off remaining photoresist
‹
• Use mixture of acids called piranah etch
‹
‹
n-well is formed with diffusion or ion implantation
Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
Necessary so resist doesn’t melt in next step
‹
Ion Implantation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si
SiO2
SiO2
p substrate
n well
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 49
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Strip Oxide
‹
‹
‹
Topic 2 - 50
Polysilicon
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
‹
Deposit very thin layer of gate oxide
• < 20 Å (6-7 atomic layers)
‹
Chemical Vapor Deposition (CVD) of silicon layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
n well
p substrate
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 51
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 52
Polysilicon Patterning
‹
Self-Aligned Process
Use same lithography process to pattern polysilicon
‹
‹
Use oxide and masking to expose where n+ dopants should be diffused
or implanted
N-diffusion forms nMOS source, drain, and n-well contact
Polysilicon
n well
Polysilicon
Thin gate oxide
p substrate
n well
p substrate
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 53
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
N-diffusion
‹
‹
‹
Topic 2 - 54
N-diffusion cont.
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates because it doesn’t
melt during later processing
n+ Diffusion
‹
‹
‹
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n+
n+
n+
n well
p substrate
n well
p substrate
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 55
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 56
N-diffusion cont.
‹
P-diffusion
Strip off oxide to complete patterning step
n+
‹
n+
Similar set of steps form p+ diffusion regions for pMOS source and drain
and substrate contact
n+
p+ Diffusion
n well
p substrate
p+
n+
n+
p+
p+
n+
n well
p substrate
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 57
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Contacts
‹
‹
‹
Topic 2 - 58
Metalization
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
‹
‹
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
M e ta l
Contact
Metal
Thick field oxide
p+
n+
n+
p+
p+
Thick field oxide
n+
p+
n+
n+
n well
p+
n+
n well
p substrate
MOS Theory, SPICE, Fabrication
p+
p substrate
Introduction to Digital Integrated Circuit Design
Topic 2 - 59
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 60
Outline
‹
Layout
‹
MOS transistors
‹
‹
SPICE simulation
‹
‹
CMOS fabrication process
‹
Layout rules
Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power)
Feature size f = distance between source and drain
• Set by minimum width of polysilicon
‹
‹
‹
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design rules
Express rules in terms of λ = f/2
• E.g. λ = 0.3 μm in 0.6 μm process
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 61
MOS Theory, SPICE, Fabrication
Design Rules
‹
‹
‹
Introduction to Digital Integrated Circuit Design
Topic 2 - 62
CMOS Process Layers
Interface between designer and process engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
• scalable design rules: lambda parameter
• absolute dimensions (micron rules)
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 63
Layer
Color
Well (p,n)
Yellow
Active Area (n+,p+)
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
MOS Theory, SPICE, Fabrication
Representation
Introduction to Digital Integrated Circuit Design
Topic 2 - 64
Intra Layer Design Rules
0
or
6
Well
Different Potential
Transistor
Same Potential
Transistor Layout
2
9
Polysilicon
1
2
10
3
Contact
or Via
Hole
3
3
Metal1
Active
2
2
2
Select
3
2
3
4
Metal2
5
3
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 65
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Via’s and Contacts
Topic 2 - 66
Select Layer
2
2
4
Via
1
2
1
1
5
Metal to
1
Active Contact
3
Metal to
Poly Contact
3
Select
3
3
2
2
2
5
2
Well
Substrate
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 67
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 68
CMOS Inverter Layout
In
GND
Summary
‹
MOS transistor: majority carrier device – building block of integrated
circuits
‹
SPICE: popular circuit level simulator that applies nodal analysis of
circuit
‹
CMOS transistors are fabricated on silicon wafer
VD D
A
A’
• Lithography process
• Different materials are deposited or etched in each step
Out
(a) Layout
‹
A
Layout rules: contract between IC designer and process engineer
• Guidelines for constructing process masks
A’
n
p-substrate
n+
p+
Field
Oxide
(b) Cross-Section along A-A’
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 69
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Topic 2 - 70