Sequential Circuit Design
Section 5-5
State Machines Design Procedure
1. Specification- obtain (produce) problem
description
2. Formulation - Obtain a state diagram
or state table
3. State Assignment - Assign binary codes
to the states
4. Flip-Flop Input Equation Determination
a) Select flip-flop types
b) Derive equations of inputs to the flip-flops
from next state entries in the table
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State Machines Design Procedure (continued)
5. Output Equation Determination Derive output equations from output
entries in the table
6. Optimization - Optimize the equations
7. Technology Mapping –
a) Find circuit from equations
b) Map to flip-flops and gate technology
8. Verification - Verify correctness of final
design
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State Machines Design Procedure;
Example: Sequence Recognizer Specification
Example 5-3 (pp. 233-235)
1. Specification- obtain (produce) problem



description
Circuit has input, X, and output, Z
Recognizes sequence 1101 on X
Specifically, if X has been 110 and next bit is
1, make Z high
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Understand the problem specifications:
Sequence Recognizer
 Sequential machine recognizes the
sequence 1101
 The sequence 1111101 contains 1101
Sequential machine must remember
that the first two one's have occurred
as it receives another bit.
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Understand the problem specifications:
Sequence Recognizer II
 Also, the sequence 1101101 contains 1101
as both an
• initial subsequence 1101101
• final subsequence
1101101
 The sequence 1101 must be recognized each
time it occurs in the input sequence.
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State Machines Design Procedure;
Example: Sequence Recognizer Formulation
2. Formulation - Obtain a state diagram or
state table
 States remember past history
• Must remember we’ve seen 11 as machine
receives another bit
• Must remember we’ve seen 110 when
another bit comes along
• There is more to remember….
 Tell me one necessary state
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Beginning State
• System starts in some state, A
A
8
First 1
• If 1 appears, move to next state B
• B recognizes (remembers) that 1
was received
Input / Output
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Second 1
• New state, C
• C remembers that 11 was received
10
Next a 0
• If 110 has been received, go to D
• D remembers that 110 was received
• Next 1 will generate a 1 on output Z
11
What else?
• What happens to arrow on right?
♦ Must go to some state.
♦ Where?
• Remember we’ve just seen 01
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You must cover every possibility
• You must have every possibility out of
every state
• In this case, just two possibilities: X = 0
or 1
• We fill in other cases on the white
board
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Fill in
Remembers that
{a single “1”
sequence
occurred }
Remembers that
{a “11”
sequence
occurred }
Remembers
that a {“110”
sequence
occurred}
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Answer
Remembers: No proper sub-sequence
of the sequence 1101 has occurred
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Recognize 1101 (continued)
A
1/0
B
1/0
C
0/0
D
1/1
 The states have the following abstract
meanings:
• A: No proper sub-sequence of the sequence
has occurred.
• B: The sub-sequence 1 has occurred.
• C: The sub-sequence 11 has occurred.
Chapter 5 - Part 2
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Example: Recognize 1101 (continued I)
A
1/0
B
1/0
C
0/0
D
1/1
• D: The sub-sequence 110 has occurred.
• The 1/1 on the arc from D to B means that
the last 1 has occurred and thus, the
sequence is recognized.
Chapter 5 - Part 2
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Find State Table
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3. State Assignment
 Each of the m states must be assigned a
unique binary code
• Sequence Recognizer: m=4 (A, B, C, D)
 Minimum number of bits required is n
such that
n ≥ log2 m
where x is the smallest integer ≥ x
 In general, there can be 2n - m unused
states
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State Assignment for the Sequence
Recognizer: Example 5-5 p. 239
Present
State
A
B
C
D
Next State
x=0 x=1
A
B
A
C
D
C
A
B
Output
x=0 x=1
0
0
0
0
0
0
0
1
 # of needed codes = m = 4;
 How may assignments of codes are
possible with 2 bits?
 4  3  2  1 = 24
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State Assignment – (continued)
 Let us choose the code assignment :
A=00,B=01,C=11,D=10
 The resulting coded state table:
Present Next State
Output
State x = 0 x = 1 x = 0 x = 1
00
00 01
0
0
01
00 11
0
0
11
10 11
0
0
10
00 01
0
1
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4. Find Flip-Flop Input and
Output Equations
 Assume D flip-flops, outputs labeled A, B
 Obtain K-maps for DA, DB, and Z:
DA
X
0 0
0 1
B
1 1
A
0 0
DB
X
0 1
0 1
B
0 1
A
0 1
Z
X
0 0
0 0
B
0 0
A
0 1
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6. Optimization:
 Performing two-level optimization:
DA
X
0 0
0 1
B
1 1
A
0 0
DB
X
0 1
0 1
B
0 1
A
0 1
Z
X
0 0
0 0
B
0 0
A
0 1
DA = AB + XB
DB = X
Z = XAB
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7. Map Technology
 DA = AB + XB
DB = X
Z = XAB
 Initial Circuit:
D
X
D
Clock
A
C
R
B
C
R
Reset
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Mapped Circuit - Final Result
Library:
 D Flip-flops
with Reset
A
D
C
R
 NAND gates
with up to 4
inputs and
inverters
Z
X
Clock
B
D
C
R
Reset
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