Making Petri nets
friendlier to designers
Jordi Cortadella
(Universitat Politècnica de Catalunya, Barcelona)
STRUCTURE 2017
Outline
• Friendly specification models for
asynchronous circuits
• Mining friendly process specifications
Structure 2017
Friendly Petri nets
2
Friendly specification models for
asynchronous circuits
Jordi Cortadella, Alberto Moreno, Danil Sokolov,
Alex Yakovlev, and David Lloyd.
Waveform transition graphs: a designer-friendly
formalism for asynchronous behaviours.
Int. Symp. on Advanced Research in Asynchronous
Circuits and Systems, May 2017.
Specification of an asynchronous circuit
Minimalist Petri net (Signal Transition Graph)
Inputs
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Outputs
Friendly Petri nets
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Asynchronous controllers
Source: Sokolov et al., Towards asynchronous power management, FTFC 2014.
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Friendly Petri nets
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Specification formalisms: process algebras
Set Env = { rinp, routp, ainp, aoutp };
CCS:
agent Env-L = rin.’rinp.Env-Lw;
agent Env-Lw = ainp.(‘ain.Env-L + ainp.Env-Lw);
agent Env-R = routp.(‘rout.aout.’aoutp.Env-R
+ routp.Env-R);
agent Implementation = (Env-L | Circuit | Env-R) \ Env;
Balsa:
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procedure buffer
(input i: byte;
output o: byte) is
variable x : byte
begin
loop
i -> x ; o <- x
end
end
Friendly Petri nets
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Specification formalisms: Burst Mode
s1
a+, b-/
x-, y+
s2
No input/output concurrency
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Friendly Petri nets
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Specification formalisms: STGs
Bus
Data
Transceiver
Device
d
dsr
dsw
dtack
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VME Bus
Controller
lds
ldtack
Friendly Petri nets
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STGs are great !
• Any asynchronous behaviour can be specified.
• Implementation properties can be easily checked:
– Consistency, output persistence, state encoding.
• There is a solid automatic synthesis flow from
STGs to circuits (e.g., petrify, MPSAT):
– State encoding
– Logic synthesis for speed-independent circuits
– Logic decomposition and technology mapping
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Friendly Petri nets
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Control specification
Ri
Ao
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FIFO
cntrl
Ro
Ai
Friendly Petri nets
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
10
Control specification
Ri
Ao
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FIFO
cntrl
Ro
Ai
Friendly Petri nets
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
11
Control specification
Ri
Ao
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FIFO
cntrl
Ro
Ai
Friendly Petri nets
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
12
Control specification
Ri
Ao
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FIFO
cntrl
Ro
Ai
Friendly Petri nets
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
13
Control specification
Ri
Ao
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FIFO
cntrl
Ro
Ai
Friendly Petri nets
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
14
Control specification
Ri
Ao
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FIFO
cntrl
Ro
Ai
Friendly Petri nets
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
15
Control specification
Ri
Ao
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FIFO
cntrl
Ro
Ai
Friendly Petri nets
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
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Control specification
Ri
Ao
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FIFO
cntrl
Ro
Ai
Friendly Petri nets
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
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Control specification
Ri
Ao
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FIFO
cntrl
Ro
Ai
Friendly Petri nets
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
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Control specification
Ri
Ao
Structure 2017
FIFO
cntrl
Ro
Ai
Friendly Petri nets
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
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Control specification
Ri
FIFO
cntrl
Ao
Ro
Ai
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
Ri
Ao
C
C
Ro
Ai
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Friendly Petri nets
20
Trying to persuade engineers (the cruel reality)
petri what …?
tokens?
Yeah! Signal Transition Graphs
are extremely useful.
They are based on Petri nets!.
They have places, transitions, and
some tokens that flow, …
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Friendly Petri nets
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We need a simpler formalism
STG experts
STGs
?
Non-expert engineers
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Wish list for the specification model
• Easy adoption.
STGs
• Powerful
– maybe a little bit less than STGs
– but more than Burst Mode
?
• Efficient: use logic synthesis
(Boolean minimization).
• Reuse the existing
infrastructure for STGs.
Structure 2017
Friendly Petri nets
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Engineers understand waveforms
Source: Xilinx LogiCORE IP FIFO Generator
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Friendly Petri nets
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Multiple waveforms (modes of operation)
Choice
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Expressive power
STGs
• Causality and concurrency
between events.
• Choice (modes of operation):
– AMBA bus: read/write cycle.
?
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• Proposal (our sacrifice):
– Concurrency and choice
mutually exclusive.
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Expressive power
Not allowed
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Example: Buck controller
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Mode: UV before ZC
zc
uv
oc
gp
gp_ack
gn
gn_ack
no concurrency
no concurrency
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Friendly Petri nets
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Waveform Transition Graph (WTG)
(nodal states)
WF
WF
choice-free & acyclic
WF
WF
WF
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Friendly Petri nets
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Waveform Transition Graph (WTG)
(nodal states)
WF
WF
choice-free & acyclic
WF
WF
WF
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Nodal state in reachability graph
nodal state
(no concurrency)
w
d
x
x
e
e
w
d
z
a
y
c
b
y
b
c
z
• Only nodal states can have choice
• For timed verification: all counters to zero
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Friendly Petri nets
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Waveform Abstraction
Silent transitions might be acceptable
Causality &
Concurrency
(choice-free)
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WTG of a buck controller
WF1
WF3
WF2
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Concurrency and choice
Bus
Data
Transceiver
D
DSr
DSw
Device
LDS
VME Bus
Controller LDTACK
DTACK
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Friendly Petri nets
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Concurrency and choice
DSr
Bus
Data
Transceiver
D
DSr
DSw
DTACK
LDS
VME Bus
Controller LDTACK
LDS
Device
LDTACK
D
DTACK
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Friendly Petri nets
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Concurrency and choice
Bus
Data
Transceiver
D
DSr
DSw
Device
LDS
VME Bus
Controller LDTACK
DTACK
Structure 2017
Friendly Petri nets
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WTG for the VME bus controller
WF read
WF write
Structure 2017
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WTG: expressive power
STG
WTG
BM
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Friendly Petri nets
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BM vs. WTG vs. STG
STG
BM
WTG
S1
a+,b-/
x-,y+
S2
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Friendly Petri nets
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Structural properties of SC WTGs
choice-free & acyclic
WF
WF
WF
WF
• Reachability (conjecture):
𝑀 = 𝑀0 + 𝐴𝜎
WF
•
•
•
•
Live
Safe
Abstraction: one State Machine
Every cycle of the RG contains
at least one nodal state
Structure 2017
• Negative result (not tragic):
Safe Marked Graphs  WTG
Friendly Petri nets
WF
(acyclic)
41
Not every safe Marked Graph is a WTG
a
b
x
y
b
y
a
u
v
x
v
u
Every state is at one
side of some diamond
Structure 2017
b
y
y
y
b
x
a
b
No nodal state
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Mining friendly process
specifications
Javier de San Pedro and Jordi Cortadella.
Mining structured Petri nets for the visualization of
process behavior.
31st ACM Symposium on Applied Computing, April 2016.
Mining specifications
a
Log:
abcdeab
acdbecb
acbdeab
abcea
adec
acbec
adea
b
c
c
e
a
e
b
d
d
b
a
c
c d e
a
b
Structure 2017
d
c
b
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From LTS to Labelled Petri Net
LTS
Spaghetti models
Overfitting vs. Underfitting
LTS
Flower models ()
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Our proposal
Log slice 1
Log
Slicing
Discovery
Model
Model 1
Discovery
Log slice n
Model 1
Model 2
Model 3
Process
behavior
Process
behavior
Process
behavior
Model
Discovery
Discovery
Model n
Model
Few models, each is low-complexity
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Extracting well-structured slices
Slicing
Most frequent
behavior
Captures more
than 90% of log
Less
frequent
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Mining specifications
a
Log:
abcdeab
acdbecb
acbdeab
abcea
adec
acbec
adea
b
c
c
e
a
e
b
d
d
b
a
c
c d e
a
b
Structure 2017
d
c
b
Friendly Petri nets
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Slicing specifications
a
Log:
abcdeab
acdbecb
acbdeab
abcea
adec
acbec
adea
b
d
c
c
d
e
a
e
b
d
b
a
c
c d e
a
b
SAT
formulation
c
b
Best and Devillers:
• Characterisation of the state spaces of marked graph Petri nets
• Synthesis of live and bounded persistent systems
Petrify  Synthesis of free-choice Petri nets
Structure 2017
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Slicing specifications
a
Log:
abcdeab
acdbecb
acbdeab
abcea
adec
acbec
adea
b
c
c
e
a
e
b
d
d
b
a
c
c d e
a
b
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d
c
b
Friendly Petri nets
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Slicing specifications
Log:
abcdeab
acdbecb
acbdeab
abcea
adec
acbec
adea
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Monolithic Petri net
Friendly Petri nets
71%
29%
51
SAT model
Log:
• abce
• acbe
• adbce
a 𝑡1 = 10
𝑡2 = 0
1
d 𝑡7 = 0
b
𝑡4 = 1
0 c
c 𝑡3 = 0
b
𝑡8 = 0
b
𝑡5 = 0
e 𝑡6 = 01
𝑡10 = 0 c
c 𝑡9 = 0
b
𝑡11 = 0
e 𝑡12 = 0
• One Boolean variable per LTS transition
• 𝑡𝑖 is true if corresponding arc is selected in slice
• Every valid assignment forms an LTS slice (subset)
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Example: forward persistence
•
Forward persistence:
• If a and b exist in a LTS slice,
then a and b must exist too.
• 𝑡1 ∧ 𝑡2 → 𝑡3 ∧ 𝑡4
𝑡4 c
b
c 𝑡3
b
e 𝑡6
d
b
𝑡2
a
b
𝑡3
𝑡4
Log:
• abce
• acbe
• adbce
a 𝑡1
𝑡2
𝑡1
a
𝑡7
𝑡8
𝑡5
𝑡10 c
b
c 𝑡9
b
𝑡11
SAT constraints:
• 𝑡2 ∧ 𝑡3 → 𝑡4 ∧ 𝑡5
• 𝑡8 ∧ 𝑡9 → 𝑡10 ∧ 𝑡11
• ¬𝑡3 ∨ ¬𝑡7
e 𝑡12
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Example: forward persistency
• abce
• acbe
• adbce
•
•
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abce
acbe
•
adbce
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Example: incidenttelco
448 arcs
Petri net mined with ILP miner:
9800 crossings
100% fitness
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Example: incidenttelco
• 65 slices required for 100% fitness
• However, with the first slice only:
1st slice
15 arcs
Planar (0 cros.)
92.6% fitness
Covers most
behaviours
Original
448 arcs
9800 crossings
100% fitness
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Other examples
• Similar results in other benchmarks
– Only 1-3 slices required for >90% of behaviour
– Every slice is low visual complexity
For >95% of behaviour
Benchmark
# of slices
# of crossings
# of slices
# of crossings
documentflow
1
0
4
8
fhmilu
1
4
1
4
fhmn5
1
1
1
1
incidenttelco
1
0
2
1
kim
1
0
2
0
purchasetopay
1
0
1
0
receipt
1
3
1
3
tsl
3
3
10
9
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Conclusions
• We need to expand the social circle of Petri nets:
– Asynchronous circuits
– Process/Specification mining
– … and many other domains
• Simple structures contribute to sympathise with Petri nets:
– For specification (WTG)
– For analysis and visualisation (Petri net slices)
• The structural theory of Petri nets is an essential guidance:
– “Nice” commonly means “visually friendly”
– Correlation between structural properties and visualisation
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