TABLE OF CONTENTS
INTRODUCTION: ................................................................................................................................................... 2
Ternary adder: .................................................................................................................................................. 2
2. RTL Synthesis using Synopsis Design Vision: ................................................................................................... 4
2.1 Synthesis using design vision : ................................................................................................................... 5
2.2 Steps to synthesize:.................................................................................................................................... 5
3. Equivalence Checking in Formality: ................................................................................................................. 6
3.2Steps to Check Equivalence in Formality:................................................................................................... 7
3.3Snapshots and Inference............................................................................................................................. 7
4. Equivalence Checking using Cadence Conformal: .......................................................................................... 13
4.2 Steps to Check Equivalence in conformal: ................................................................................................ 13
4.3 Snapshots and Inference: ........................................................................................................................ 14
INTRODUCTION:
Formal verification is the process of checking whether a design satisfies some properties. Formal
verification use mathematical reasoning to verify that design intent (spec) is preserved in
implementation (RTL). Formal verification, algorithmically and exhaustively explores all possible
input values over time. The process of verification is done by presenting a formal proof on an
abstract mathematical model of the system, and the relation between the model and the nature
of the system being known by the development. [3] Formal Equivalence Checking tool is a part
of EDA (Electronic Design Automation), generally used during the development of digital
integrated circuits, to formally prove that two representations of a circuit design exhibit exactly
the same behavior. Some of the current commercial equivalence checking tools are Chrysalis:
Design Verifier, Synopsys: Formality, Cadence: Conformal and Affirma, Verysys : Tornado, AHL:
Checkoff-E.[3] In this project we have used formal checking tools : "Synopsys Formality" and
"Cadence Conformal Logic Equivalence Checker" for doing the verification of the design obtained
through the synthesis of the given design using "Synopsis Design Vision".
Ternary adder:
Ternary adder is an adder with three inputs performing s = x+y+z, for the Altera and Xilinx
platforms. The Altera core (ternary_adder_altera.vhd) is a high-level implementation using the
'+' operator. However, the ternary subtract operations (x-y +z, x+y -z and x-y-z) are not supported
by a high-level description; so this is realized by extending the word size of the ternary adders
and setting the lower bits to appropriate constant values. They can be mapped very resource
efficient for all Altera FPGAs providing adaptive logic modules (ALMs), today, these are the Arria
I, II, V and Stratix II-V FPGAs.
The implementation uses a carry save adder (CSA) tree with three inputs and a final ripple carry
adder as vector merging adder (VMA). One stage of full adders (FAs) is used to realize a 3:2
compressor, i. e., the three input bit vectors are compressed to two bit vectors which are
obtained by the sum and carry outputs. A second stage of FAs merges these two bit vectors to a
single result. The 3:2 compressor can be directly mapped to the ALM LUT, realizing the sum si =
xi (xor) yi (xor) zi and carry ci = xiyi +xizi +yizi. The full adders of the ALM are used for the VMA.
To include both stages in a single ALM stage, each ALM has to be configured to the shared
arithmetic mode [BLSY09] in which the output of one LUT is connected to the FA input of the next
higher bit.
Generic
Input_word_size
Type
integer
Default
10
Description
Input word size of the
inputs x, y and z. The
output word size is
automatically set to
input_word_size+2
subtract_y
boolean
false
subtract_z
boolean
false
use_output_ff
boolean
true
Input y is negated,
realizing s = x -y ± z
Input z is negated,
realizing s = x ± y - z
If true, the adder uses
ip ops at the output
(without extra slice or
ALM resources)
Table 1: Description of the generics
Generic
clk_i
Direction
In
Type
Sl
Word size
1
rst_i
In
Sl
1
x_i
y_i
z_i
sum_o
In
In
In
out
Slv
Slv
Slv
slv
input_word_size
input_word_size
input_word_size
input_word_size +2
Table 2: Description of the port
Description
Clock input (used when
use_output_ff=true)
Reset input (used when
use_output_ff=true)
Input x
Input y
Input z
Sum output s
2. RTL SYNTHESIS USING SYNOPSIS DESIGN VISION:
It is a process by which an abstract form of desired circuit behaviour, the Register Transfer File (RTL), is
turned into a design implementation in terms of logic gates using a synthesis tool. Register-transfer-level
abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level
representations of a circuit, from which lower-level representations and ultimately actual wiring can be
derived.[5] In our project we synthesis the given RTL "fpu_sub.vhd" to a gate level design using the Synopsis
design vision software. Synopsis design compiler (Design vision) is a powerful tool designed by Synopsis to
synthesize the RTL, Structural or Behavioral level designs to gate level design. Design Vision has the graphical
user interface (GUI) like Design Compiler and other Synopsys logic synthesis tools, and it supports most of
gate-level netlist formats.
2.1 Synthesis using design vision :
Design vision is a user friendly compiler which works into two modes simultaneously. It provide
user to work in command mode or graphical mode or in both the modes simultaneously. This
feature makes it more users friendly
2.2 Steps to synthesize:
The following steps are involved in the setting up of Synopsys design compiler.

First we need to create a separate directory by typing the command-- “mkdir synopsys” .

Change the directory to Synopsys by--“cd synopsys”.

Source the environment setup--“source /CMC/ENVIRONMENT/synopsys.env”.

Copy the environment setup file in to the Synopsys directory

cp /CMC/tools/synopsys/syn/admin/setup/ .synopsys_dc.setup.class.db.synopsys_dc.setup

Starting the DC GUI interface by typing the command--“design_vision” & in the terminal box.

Observe the setup library files by opening the “File=>Setup” option.

Now, we need to load the design via “File=>Read menu”.

Next, select the top level design module via “File=>Analyze=>Add”.

Elaborate the design via “File=>Elaborate”.

Now, we need to check the design by selecting the option-“Design=>Check Design”.

If 1 is generated it implies that the design checking command is completed successfully and there
were no errors in the design. [6]

The complier will synthesize all the files included and we will obtain a gate level file "taa_syn.vhdl"
3. EQUIVALENCE CHECKING IN FORMALITY:
Formality is a functional equivalence checking tool from synopsys. Formality identifies the problem areas and
displays them in both schematics and HDL source views.

Green –this color is used to show cells ,ports and pins in their normal state

Red -This color is used to show all error candidate objects

Yellow – this color is used to show selection , it overrides any other attribute color

Cyan- this color is used to show nets in their normal state

White – this color is used to for names of cells ,nets ,ports and pins as well as any logic
Figure 1: Synopsys formality basic idea
Formality is an equivalence-checking (EC) solution designed by Synopsys that uses formal, static
techniques to determine if two versions of a design are functionally equivalent or not. Formality
supports optimizations and provides the highest quality of results that are fully verifiable.
Formality’s easy-to-use, flow-based graphical user interface and auto-setup mode helps even
new users successfully complete verification in the shortest possible time. [6]
3.2Steps to Check Equivalence in Formality:
The steps involved in the setting up of Formality checking tools is as follows:
1. First, create a work directory by typing the command in the terminal window of
2. LINUX prompt—“mkdir formality”.
3. Change the directory to formality—“cd formality”.
4. Next, sourcing the formality environment script as—“source /CMC/ENVIRONMENT/formality.env”.
5. Now, start the formality by typing-formality & at the terminal window.
6. Then, load the library file--class.db.
7. Now, load the designs in Reference and Implemented sections.
8. Next, click on ‘Setup’.
9. Click on ‘Run Matching’ button. We can see the results in the formality window.
10. Next, click on ‘Verify’ button. The verification process starts and after completion of the verification
process the results are shown in the formality console.
11. Debug-if the verification fails, we need to debug the design and find out the errors and resolve them.
[7]
3.3Snapshots and Inference
After doing the environment setup where we load the reference file and the buggy
implementation file, we verify the design. The verification failed and it provide the following
result that the buggy design contains 5 unmatched points. Those 20 failing points might be due
to multiple errors associated with single bug in the design. To find the bug in the design we
selected first failing points & we diagnose that point to find errors in particular component. The
following is the list of the failing points along with their register numbers.
Figure 2 matching and verification
Next we compare the schematics of both the reference and the implementation. We found errors by
comparing schematics.
Figure 3 set ternary_adder_add_0 as top module in reference
Figure 4 set ternary_adder_add_0 as top module in Implementation
Figure 5 Verification failed 5 failing points (add_0)
We then click on the bug and view its schematic to locate the bug.
BUG1: Reference
BUG1: Implementation
Figure 6 Start again with a new bug /new failing points
BUG2: Reference
BUG2: Implementation
Figure 7: Set ternary_adder_add_1 as top module in reference
Figure 8: Set ternary_adder_add_1 as top module in reference
Figure 9: One unmatched point/Failing point
Figure 10: Diagnose and find error using logic cones
BUG3: Reference
BUG3: Implementation
Figure 11 Verification succeeded
4. EQUIVALENCE CHECKING USING CADENCE CONFORMAL:
Conformal is a powerful equivalence checking tool developed by Cadence.it can provide formal proof that the
outputs from synthesis matches the original RTL code. It can do all the checking without any simulation. This
tool is a favorite option among the industries for equivalence checking of the gate level designs. It provides a
user friendly interface, light in memory, fast in speed and reliable solution for equivalence checking. The golden
design refers to the original “RTL net list” which refers for the comparison and the revised design is the
“synthesized gate level net list”. [8]
4.2 Steps to Check Equivalence in conformal:
The following steps are used in-order to verify the designs in conformal checking tool.

Create a work directory called conformal-mkdir conformal. Change the directory to conformal by
typing-cd conformal.

Now, source the environment script-source /CMC/ENVIRONMENT/conformal.env.

For starting conformal tool type this command-LEC –XL .

Load the designs in to Golden and Revised options in the conformal directory.

We also need to load the library file called-class.lib.

Now, start the verification process by clicking the LEC option on the top right corner of the conformal
window.
Figure 8Flow chart conformal
4.3 Snapshots and Inference:
After selecting the LEC option, a table is displayed on the conformal window showing the PI (Primary Inputs)
and PO (Primary Outputs) in both the golden and revised designs. If they have the same number of inputs
and outputs then they are equal. In-order to run the equivalence checker, select “Run=>Compare”. The two
designs are now reduced into canonical representations and then checks if they are equal.
Figure 9 Mapping manager
BUG1 U51 un-identical (nand instead of xnor)
BUG2 U36 un-identical (xnor instead of xor)
BUG3: Golden U38 (un-identical)
BUG3: Revised U38 (un-identical)
Figure 10BUG4: U47 un-identical (xor instead of or)