Dr. Ambedkar Institute of Technology
(An Autonomous Institution affiliated to VTU Belgaum)
DEPARTMENT OF ELECTRONICS & INSTRUMENTATION ENGINEERING
SCHEME OF TEACHING AND EXAMINATION 2016-2018
M.Tech in ELECTRONICS
I SEMESTER
Subject
Code
ELD11
ELD12
ELD13
ELD14
ELD15X
ELDL16
ELDS17
ELDM18
Total
Title
Advanced Engineering
Mathematics
VLSI Design
Advanced Embedded System
Digital Circuit and Logic
Design
Elective-1
Digital Electronics Lab -1
Technical Seminar
Mini project
Subject Code
ELD151
ELD152
ELD153
ELD154
Teaching
Departme
nt
Maths
Teaching hours/week
L
03
EI
EI
EI
04
04
EI
EI
EI
EI
04
20
03
ELECTIVE-1
Title of the Subject
Digital System Design using Verilog
Transformation Techniques
ASIC Design
Wireless and Adhoc Networks
1
Duration
(hrs)
T
P
Credits
02
00
04
00
00
02
00
00
00
04
04
04
03
03
00
00
04
00
4
00
06
04
02
02
02
26
03
03
03
03
24
03
03
Examination
Theory/
Total
CIE Practical
Marks
SEE
50
50
100
50
50
50
50
50
50
100
100
100
50
50
50
50
400
50
50
50
50
400
100
100
100
100
800
Dr. Ambedkar Institute of Technology
(An Autonomous Institution affiliated to VTU Belgaum)
DEPARTMENT OF ELECTRONICS & INSTRUMENTATION ENGINEERING
SCHEME OF TEACHING AND EXAMINATION 2016-2018
M.Tech in ELECTRONICS
II SEMESTER
L
T
P
Credits
Duration
(hrs)
EI
EI
EI
EI
03
04
03
04
02
00
02
00
00
00
00
00
04
04
04
04
03
03
03
03
Examination
Theory/
Total
CIE Practical
Marks
SEE
50
50
100
50
50
100
50
50
100
50
50
100
EI
EI
EI
EI
04
02
20
00
00
04
00
04
00
04
08
04
02
02
02
26
03
03
03
03
24
50
50
50
50
400
Title
Teaching
Departme
nt
ELD21
ELD22
ELD23
ELD24
Advanced DSP
Coding Theory
Soft computing
Real Time Operating System
ELD25
ELD26X
ELDL27
ELDM28
Total
Research Methodology
Elective-2
Digital Electronics Lab -2
Mini project
Subject
Code
Subject Code
ELD 261
ELD 262
ELD 263
ELD 264
Teaching hours/week
ELECTIVE-2
Title of the Subject
Adaptive Signal Processing
Multimedia Communication
Advances in video and image processing
Data Encryption Techniques
2
50
50
50
50
400
100
100
100
100
800
Sub Title : VLSI DESIGN
Sub Code: ELD12
No. of Credits:4 = 4:0:0(L-T-P) No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
Course Objectives: This course will enable students to:
1. Explain VLSI Design Methodologies
2. Learn Static and Dynamic operation principles, analysis and design
of inverter circuit.
3. Infer state of the art Semiconductors Memory circuits.
4. Outline the comprehensive coverage of Methodologies and Design practice
that are used to reduce the Power Dissipation of large scale digital circuits.
Illustrate VLSI and ASIC design.
UNIT
NO.
1
2
3
4
SYLLABUS CONTENT
No. of
TEACHING
HOURS
MOS Transistor: The Metal Oxide Semiconductor (MOS) Structure, The
MOS System under External Bias, Structure and Operation of MOS
Transistor, MOSFET Current-Voltage Characteristics, MOSFET Scaling
10 Hours
and Small-Geometry Effects.
MOS Inverters-Static Characteristics: Introduction, Resistive-Load
Inverter, Inverters with n- Type MOSFET Load.
MOS Inverters-Static Characteristics: CMOS Inverter. MOS
Inverters: Switching Characteristics and Interconnect Effects:
Introduction, Delay-Time Definition, Calculation of Delay Times,
Inverter Design with Delay Constraints, Estimation of Interconnect
Parasitic, Calculation of Interconnect Delay, Switching
11 Hours
Power Dissipation of CMOS Inverters.
Semiconductor Memories: Introduction, Dynamic Random Access
Memory (DRAM), Static Random Access Memory (SRAM), Nonvolatile
Memory, Flash Memory, Ferroelectric Random Access Memory (FRAM).
10 Hours
Review of MOS Circuits: MOS and CMOS static plots, switches,
comparison between CMOS and BI - CMOS. MESFET and MODFET
operations, quantitative description of MESFETS.MIS systems in
equilibrium, under bias, small signal operation of MESFETS and
MOSFETS.
10 Hours
Short Channel Effects and Challenges to CMOS: Short channel
effects, scaling theory, processing challenges to further CMOS
miniaturization
3
5
Beyond CMOS: Evolutionary advances beyond CMOS, carbon
Nanotubes, conventional vs. tactile computing, computing,
molecular and biological computing Mole electronics-molecular
Diode and diode- diode logic.
Super Buffers and Bi-CMOS: Introduction, RC delay lines, super
buffers- An NMOS super buffer, tri state super buffer and pad 11 Hours
drivers, CMOS super buffers, Dynamic ratio less inverters, large
capacitive loads, pass logic, designing of transistor logic, General
functional blocks -NMOS and CMOS functional blocks.
Note: Unit 4 and Unit 5 have internal choice.
Course outcomes: After studying this course, students will be able to:
1. Analyse issues of On-chip interconnect Modelling and Interconnect delay
calculation.
2. Analyse the Switching Characteristics in Digital Integrated Circuits.
3. Use the Dynamic Logic circuits in state of the art VLSI chips.
4. Study critical issues such as ESD protection, Clock distribution, Clock
buffering, and Latch phenomenon.
5. Use Bipolar and Bi-CMOS circuits in very high speed design.
Text Book:
Sung Mo Kang & Yosuf Leblebici, “CMOS Digital Integrated Circuits: Analysis
and Design”, Tata McGraw-Hill, Third Edition.
Reference Books:
1. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design: A System
Perspective”, Second Edition, Pearson Education (Asia) Pvt. Ltd. 2000.
2. Wayne, Wolf, “Modern VLSI Design: System on Silicon” Prentice Hall
PTR/Pearson Education, Second Edition, 1998.
3. Douglas A Pucknell & Kamran Eshragian, “Basic VLSI Design”, PHI 3rd
Edition (original Edition – 1994).
4
Sub Title : ADVANCED EMBEDDED SYSTEM
Sub Code: ELD13
No. of Credits:4 = 4:0:0(L-T-P) No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
Course Objectives: This course will enable students to:
 Understand the basic hardware components and their selection method
based on the characteristics and attributes of an embedded system.
 Describe the hardware software co-design and firmware design approaches
 Explain the architectural features of ARM CORTEX M3, a 32 bit
microcontroller including memory map, interrupts and exceptions.
 Program ARM CORTEX M3 using the various instructions, for different
applications
UNIT
NO.
1
2
3
4
5
SYLLABUS CONTENT
Embedded System: Embedded vs General computing system,
classification, application and purpose of ES. Core of an Embedded
System,
Memory,
Sensors,
Actuators,
LED,
Opto
coupler,
Communication Interface, Reset circuits, RTC, WDT, Characteristics
and Quality Attributes of Embedded Systems
Hardware Software Co-Design, embedded firmware design approaches,
computational models, embedded firmware development languages,
Integration and testing of Embedded Hardware and firmware,
Components in embedded system development environment (IDE), Files
generated during compilation, simulators, emulators and debugging (
ARM-32 bit Microcontroller: Thumb-2 technology and applications of
ARM, Architecture of ARM Cortex M3, Various Units in the architecture,
General Purpose Registers, Special Registers, exceptions, interrupts,
stack operation, reset sequence
Instruction Sets: Assembly basics, Instruction list and description,
useful instructions, Memory Systems, Memory maps, Cortex M3
implementation overview, pipeline and bus interface
No. of
TEACHING
HOURS
10 Hours
11 Hours
11 Hours
10 Hours
Exceptions, Nested Vector interrupt controller design, Systick Timer, 10 Hour
Cortex-M3 Programming using assembly and C language, CMSIS
Note: Unit 2 and Unit 3 have internal choice.
5
Course Outcomes:
After studying this course, students will be able to:
 Understand the basic hardware components and their selection method
based on the characteristics and attributes of an embedded system.
 Explain the hardware software co-design and firmware design approaches.
 Acquire the knowledge of the architectural features of ARM CORTEX M3, a
32 bit microcontroller including memory map, interrupts and exceptions.
 Apply the knowledge gained for Programming ARM CORTEX M3 for different
applications.
Text Books:
1. K. V. Shibu, "Introduction to embedded systems", TMH education Pvt. Ltd.
2009
2. Joseph Yiu, “The Definitive Guide to the ARM Cortex-M3”, 2nd edn, Newnes,
(Elsevier), 2010.
Reference Book:
James K. Peckol, "Embedded systems- A contemporary design tool", John Wiley,
2008.
6
Sub Title : DIGITAL CIRCUITS AND LOGIC DESIGN
Sub Code: ELD14
No. of Credits:4 = 3:2:0(L-T-P) No. of Lecture hours / week : 5Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 65
Course Objectives: This course will enable students to:




UNIT
NO.
1
2
3
4
Understand the concepts of sequential machines
Design Sequential Machines/Circuits
Analyze the faults in the design of circuits
Apply fault detection experiments to sequential circuits
No of Hours
SYLLABUS CONTENT
Theory
Tutorial
Threshold Logic: Introductory Concepts, Synthesis of
Threshold Networks, Capabilities, Minimization, and
Transformation of Sequential Machines: The Finite- State
Model, Further Definitions, Capabilities.
08 Hours
05 Hours
Fault Detection by Path Sensitizing, Detection of Multiple
Faults, Failure-Tolerant Design, Quadded Logic, Reliable
Design and Fault Diagnosis Hazards: Fault Detection in
Combinational Circuits.
08 Hours
05 Hours
Fault-Location Experiments, Boolean Differences, Limitations
of Finite – State Machines, State Equivalence and Machine
Minimization, Simplification of Incompletely Specified
Machines.
08 Hours
05 Hours
Structure of Sequential Machines: Introductory Example,
State Assignments Using Partitions, The Lattice of closed
Partitions, Reductions of the Output Dependency, Input
Independence and Autonomous Clocks, Covers and
Generation of closed Partitions by state splitting, Information
Flow in Sequential Machines, ELDecompositions, Synthesis
of Multiple Machines.
08 Hours
05 Hours
Note: Unit 2 and Unit 3 have internal choice.
Course outcomes: At the end of the course, the students will be able to:

Understand the concepts of sequential machines
7


Design Sequential Machines/Circuits
Analyze the faults in the design of circuits
Apply fault detection experiments to sequential circuits
Text Book:
Zvi Kohavi, “Switching and Finite Automata Theory”, 2nd Edition, TMH.
Reference Books:
1. Charles Roth Jr., “Digital Circuits and logic Design”, 7th edn, Cengage Learning,
2014.
2. Parag K Lala, “Fault Tolerant And Fault Testable Hardware Design”, Prentice
Hall Inc. 1985.
3. E. V. Krishnamurthy, “Introductory Theory of Computer”, Macmillan Press Ltd,
1983.
4. Mishra & Chandrasekaran, “Theory of computer science – Automata, Languages
and Computation”, 2nd Edition, PHI, 2004.
Sub Title : DIGITAL SYSTEM DESIGN USING VERILOG
Sub Code: ELD151
No. of Credits:4 = 4:0:0(L-T-P) No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
Course objectives: This course will enable students to:
 Understand the concepts of Verilog Language
 Design the digital systems as an activity in a larger systems design context.
 Study the design and operation of semiconductor memories frequently used
in
application specific digital system.
 Inspect how effectively IC’s are embedded in package and assembled in
PCB’s for different application
 Design and diagnosis of processors and I/O controllers they can be used in
 embedded systems
UNIT
No. of
NO.
SYLLABUS CONTENT
TEACHING
HOURS
1
2
Introduction and Methodology: Digital Systems and Embedded
Systems, Binary representation and Circuit Elements, Real-World
10 Hours
Circuits, Models, Design Methodology.
Number Basics: Unsigned and Signed Integers, Fixed and Floating- 11 Hours
point Numbers.
Sequential Basics: Storage elements, Counters, Sequential Data paths
and Control, Clocked Synchronous Timing Methodology.
8
Memories: Concepts, Memory Types, Error Detection and Correction.
Implementation Fabrics: ICs, PLDs, Packaging and Circuit Boards,
3
11 Hours
Interconnection and Signal Integrity.
Processor Basics: Embedded Computer Organization, Instruction and 10 Hours
4
Data, Interfacing with memory.
I/O interfacing: I/O devices, I/O controllers, Parallel Buses, Serial
Transmission, I/O software.
Accelerators: Concepts, case study, Verification of accelerators.
Design Methodology: Design flow, Design optimization, Design for test 10 Hour
5
Note: Unit 3 and Unit 4 have internal choice.
Course outcomes: After studying this course, students will be able to:
1. Design embedded systems, using small microcontrollers, larger CPUs/DSPs, or
hard or
soft processor cores.
2. Design & Construct the combinational circuits using discrete gates and
programmable logic devices.
3. Describe Verilog model for sequential circuits and test pattern generation
4. Explore the different types of semiconductor memories and their usage for
specific chip design
5. Design and synthesis of different types of processor and I/O controllers that are
used in embedded system design
Text Book:
Peter J. Ashenden, “Digital Design: An Embedded Systems Approach Using
VERILOG”, Elesvier, 2010.
Reference Book:
Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition By Samir
Palnitkar.
Sub Title : TRANSFORMATION TECHNIQUES
Sub Code: ELD152
No. of Credits:4 = 4:0:0(L-T-P) No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
Course objectives:
1. Analyze transforms using Fourier analysis
2. Analyze transforms by its applications and properties.
3. Design and analyze continuous wavelet transform.
4. Design discrete wavelet transform and analyze multi-rate in wavelet transform.
5. Analyze different forms of wavelets.
9
UNIT
NO.
1
SYLLABUS CONTENT
Fourier Analysis: Vector space, Hilbert spaces, Fourier basis, FT- Limitations of
Fourier Analysis, Need for time-frequency analysis, DFT, 2D-DFT: Definition,
Properties and Applications, IDFT, Hilbert Transform, STFT
Transforms: Walsh, Hadamard, Haar and Slant Transforms, DCT, DST, KLT,–
definition, properties and applications
No. of
TEACHING
HOURS
10 Hours
11 Hours
2
Continuous Wavelet Transform (CWT): Short comings of STFT, Need for
wavelets, Wavelet Basis- Concept of Scale and its relation with frequency,
Continuous time wavelet Transform Equation- Series Expansion using Wavelets- 11 Hours
3
CWT- Tiling of time scale plane for CWT. Important Wavelets: Haar, Mexican Hat,
Meyer, Shannon, Daubechies.
Multi Rate Analysis and DWT: Need for Scaling function – Multi Resolution 10 Hours
Analysis, Two-Channel Filter Banks, Perfect Reconstruction Condition,
Relationship between Filter Banks and Wavelet Basis, DWT, Structure of DWT
4
Filter Banks, Daubechies Wavelet Function, Applications of DWT.
Special Topics: Wavelet Packet Transform, Multidimensional Wavelets, Bi5
orthogonal basis- B-Splines, Lifting Scheme of Wavelet Generation, Multi Wavelets
10 Hour
Note: Unit 3 and Unit 4 have internal choice.
Course outcomes:
1. Analyze transforms using Fourier analysis
2. Analyze transforms by its applications and properties.
3. Design and analyze continuous wavelet transform.
4. Design discrete wavelet transform and analyze multi-rate in wavelet transform.
5. Analyze different forms of wavelets.
TEXT BOOKS:
· Wavelet Transforms-Introduction theory and applications -Raghuveer M.Rao and Ajit S.
Bopardikar, Pearson Edu, Asia, New Delhi, 2003.
· “Insight into Wavelets from Theory to Practice” - Soman. K. P, Ramachandran. K.I,
Printice Hall India, First Edition, 2004.
REFERENCE BOOKS:
10
1. Fundamentals of Wavelets- Theory, Algorithms and Applications -Jaideva C Goswami,
Andrew K Chan, John Wiley & Sons, Inc, Singapore, 1999.
2. Wavelets and Sub-band Coding -Vetterli M. Kovacevic, PJI, 1995.
3. Introduction to Wavelets and Wavelet Transforms -C. Sydney Burrus, PHI, First Edition,
1997.
4. A Wavelet Tour of Signal Processing-Stephen G. Mallat, Academic Press, 2 Ed
5. Digital Image Processing – S.Jayaraman, S.Esakkirajan, T.Veera Kumar – TMH,2009
Sub Title : ASIC DESIGN
Sub Code: ELD153
No. of Credits:4 = 4:0:0(L-T-P) No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
Course objectives: This course will enable students to:
 Explain ASIC methodologies and programmable logic cells to implement
a function on IC.
 Analyse back-end physical design flow, including partitioning, floorplanning,
 placement, and routing.
 Gain sufficient theoretical knowledge for carrying out FPGA and ASIC
designs.
 Design CAD algorithms and explain how these concepts interact in ASIC
design.
UNIT
NO.
1
2
SYLLABUS CONTENT
No. of
TEACHING
HOURS
Introduction to ASICs, Full custom, Semi-custom and Programmable
ASICs, ASIC Design flow, ASIC cell libraries.
CMOS Logic: Datapath Logic Cells: Data Path Elements, Adders: Carry 10 Hours
skip, Carry bypass, Carry save, Carry select, Conditional sum,
Multiplier (Booth encoding), Data path Operators, I/O cells.
ASIC Library Design: Logical effort: Predicting Delay, Logical area and
logical efficiency, Logical paths, Multi stage cells, Optimum delay and
number of stages.
Programmable ASIC Logic Cells:
MUX as Boolean function generators, Actel ACT: ACT 1, ACT 2 and ACT
11 Hours
3 Logic Modules, Xilinx LCA: XC3000 CLB, Altera FLEX and MAX.
11
3
Programmable ASIC I/O Cells: Xilinx and Altera I/O Block.
Low-level design entry: Schematic entry: Hierarchical design,
Netlist screener.
11 Hours
ASIC Construction: Physical Design, CAD Tools.
Partitioning: Goals and objectives, Constructive Partitioning, Iterative
Partitioning Improvement, KL, FM and Look Ahead algorithms.
4
Floor planning and placement: Goals and objectives, Floor planning
10 Hours
tools, Channel definition, I/O and Power planning and Clock planning.
Placement: Goals and Objectives, Min-cut Placement algorithm,
Iterative Placement Improvement, Physical Design Flow.
5
Routing: Global Routing: Goals and objectives, Global Routing
Methods, Back-annotation. Detailed Routing: Goals and objectives,
Measurement of Channel Density, Left-Edge and Area-Routing
Algorithms. Special Routing, Circuit extraction and DRC.
10 Hour
Note: Unit 2 and Unit 3 have internal choice.
Course outcomes: After studying this course, students will be able to:
1. Describe the concepts of ASIC design methodology, data path elements, logical
effort and FPGA architectures.
2. Analyze the design of FPGAs and ASICs suitable for specific tasks, perform
design entry and explain the physical design flow.
3. Design data path elements for ASIC cell libraries and compute optimum path
delay.
4. Create floorplan including partition and routing with the use of CAD algorithms.
TextBook:
Michael John Sebastian Smith, “Application - Specific Integrated Circuits”
Addison-Wesley Professional; 2005.
Reference Books:
1. Neil H.E. Weste, David Harris, and Ayan Banerjee, “CMOS VLSI Design: A
Circuits and Systems Perspective”, 3rd edition, Addison Wesley/ Pearson
education, 2011.
2. Vikram Arkalgud Chandrasetty, “VLSI Design: A Practical Guide for FPGA and
ASIC Implementations”, Springer, 2011, ISBN: 978-1-4614-1119-2.
3. Rakesh Chadha, Bhasker J., “An ASIC Low Power Primer”, Springer, ISBN: 9781- 4614-4270-7.
12
Sub Title : WIRELESS ADHOC NETWORKS
Sub Code: ELD154
No. of Credits:4 = 4:0:0(L-T-P) No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
Course objectives:
• To explore the design space and conduct trade-off analysis between performance and resources.
• To determine suitable medium access protocols and radio hardware.
• To learn Provision quality of service, fault-tolerance, security and other dependability requirements
while coping with resource constraints.
• To explore the Ad-hoc network concepts by using network simulators.
UNIT
NO.
1
2
3
4
5
SYLLABUS CONTENT
Ad hoc Wireless Networks: Introduction, Issues in Ad hoc Wireless Networks, Ad
hoc
Wireless Internet; MAC Protocols for Ad hoc Wireless Networks: Introduction,
Issues in Designing a MAC Protocol, Design Goals of MAC Protocols,
Classification of MAC protocols, Contention-Based Protocols, Contention-Based
Protocols with Reservation Mechanisms, Contention-Based Protocols with
Scheduling Mechanisms, MAC Protocols that Use Directional Antennas
Routing Protocols for Ad Hoc Wireless Networks: Introduction, Issues in
Designing a Routing Protocol for Ad hoc Wireless Networks; Classification of
Routing Protocols; Table Driven Routing Protocols; On-Demand Routing Protocols,
Hybrid Routing Protocols, Hierarchical Routing Protocols and Power-Aware
Routing Protocols
Multicast Routing in Ad hoc Wireless Networks: Introduction, Issues in
Designing a Multicast Routing Protocol, Operation of Multicast Routing Protocols,
An Architecture Reference Model for Multicast Routing Protocols, Classifications
of Multicast Routing Protocols, Tree-Based Multicast Routing Protocols and MeshBased Multicast Routing Protocols.
Transport Layer and Security Protocols for Ad hoc Networks: Introduction,
Issues in Designing a Transport Layer Protocol; Design Goals of a Transport Layer
Protocol; Classification of Transport Layer Solutions; TCP over Transport Layer
Solutions; Other Transport Layer Protocols for Ad hoc Networks; Security in Ad
hoc Wireless Networks, Issues and Challenges in Security Provisioning, Network
Security Attacks, Key Management and Secure Touting Ad hoc Wireless Networks.
Quality of Service and Energy Management in Ad hoc Wireless Networks
Introduction, Issues and Challenges in Providing QoS in Ad hoc Wireless Networks,
Classification of QoS Solutions, MAC Layer Solutions, Network Layer Solutions;
13
No. of
TEACHING
HOURS
10 Hours
11 Hours
11 Hours
10 Hours
10 Hour
Energy Management in Ad hoc Wireless Networks: Introduction, Need for Energy
Management in Ad hoc Wireless Networks, Classification of Energy Management
Schemes, Battery Management Schemes, Transmission Management Schemes,
System Power Management Schemes.
Note: Unit 3 and Unit 4 have internal choice.
Course outcomes: At the end of this course, the students will be able to:
Students will be able to
· Apply knowledge of wireless Ad-hoc networks to various application areas.
· Design, implement and maintain wireless Ad-hoc networks.
· Formulate and solve problems creatively.
· Practical knowledge acquired by hands-on session.
TEXT BOOKS:
1. C. Siva Ram Murthy & B. S. Manoj: Ad hoc Wireless Networks, 2nd Edition, Pearson
Education, 2011
REFERENCES:
1. Ozan K. Tonguz and Gianguigi Ferrari: Ad hoc Wireless Networks, John Wiley, 2007.
2. Xiuzhen Cheng, Xiao Hung, Ding-Zhu Du: Ad hoc Wireless Networking, Kluwer Academic
Publishers, 2004.
Sub Title : DIGITAL ELECTRONICS LAB -1
Sub Code: ELDL16
No. of Credits:4 = 0:0:2(L-T-P) No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
Course objectives: This laboratory course enables students to get practical
experience on the
 Design tool such as Cadence OrCAD/ OrCAD Lite /EDA tool
 Design of analog and digital circuits using the simulation tool
 FPGA Design and testing for digital circuits

Verilog programming and design of digital circuits

Design, verification and performance testing
1.Using Cadence OrCAD or OrCAD Lite or any EDA Tool, design
and verify the following:
a) 3½ Digit Digital Voltmeter
b) Monolithic function Generator
14
c) Regulated Power supplies
d) Batch counter using TTL ICs.
e) DAC and ADC
f) P, PI, PID and ON/OFF Controllers
g) Programmable Timers
h) Filters and Resonance Circuits
2. Develop Verilog Program for design and testing the following
digital circuits (for 4/8 bits) using FPGA/CPLD. Use logic
analyzer/Chipscope for the verification of results.
(Note: Programming can be done using any complier. Down load the
programs on FPGA/CPLD boards and performance testing may be
done using pattern generator (32 channels and logic analyzer
)/Chipscope pro. Implementing the above designs on
Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits.)
a. Carry skip and carry lookahead adder
b. BCD adder and subtractor
c. Array Multiplication (signed and unsigned)
d. Booth multiplication (radix-4)
e. Magnitude comparator
f. LFSR
g. Parity generator
h. Universal Shift Register
i. Sequence generation (11101 say) using Mealy/Moore FSM






Course outcomes: On the completion of this laboratory course, the
students will be able to:
Design an analog and digital systems using Cadence OrCAD, OrCAD Lite or
any
EDA tool.
Develop Verilog Programs for Digital Circuit design simulation.
Design and implement digital systems on FPGA/CPLD
Testing and validation of digital systems using Logic analyzer/Chipscope
15
Sub Title : Advance DSP
Sub Code: ELD21
No. of Credits:4= 4:0:0(L-T-P)
No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
Course objectives: – Advances in Digital Signal Processing involve variable sampling rates
and thus the multirate signal processing and hence their applications in communication systems
and signal processing. It is intended to introduce a basic course in multirate signal processing
especially meant for students of branches eligible for M Tech courses in EC related disciplines.
UNIT
NO.
No of Hours
SYLLABUS CONTENT
Theory
Tutorial
1
Introduction and Discrete Fourier Transforms: Signals,
Systems and Processing, Classification of Signals, The
Concept of Frequency in Continuous-Time and DiscreteTime Signals, Analog-to-Digital and Digital-to-Analog
Conversion, Frequency-Domain Sampling: The Discrete
Fourier Transform, Properties of the DFT, Linear Filtering
Methods Based on the DFT
08 Hours
05 Hours
2
Design of Digital Filters: General Considerations, Design of
FIR Filters, Design of IIR Filters from Analog Filters,
Frequency Transformations.
08 Hours
05 Hours
3
Multirate Digital Signal Processing: Introduction, EL
Dimation by a factor ‘D’, Interpolation by a factor ‘I’,
Sampling rate Conversion by a factor ‘I/D’, implementation
of Sampling rate conversion, Multistage implementation of
Sampling rate conversion, Sampling rate conversion of Band
Pass Signals, Sampling rate conversion by an arbitrary
factor,
08 Hours
05 Hours
4
Applications of Multirate Signal Processing, Digital Filter
banks, Two Channel Quadrature Mirror Filter banks, MChannel QMF bank
08 Hours
05 Hours
5
Adaptive Filters: Applications of Adaptive Filters, Adaptive
Direct Form FIR Filters- The LMS Algorithm, Adaptive
Direct Form Filters-RLS Algorithm.
08 Hours
05 Hours
16
Note: Unit numbers: 3& 5 will have internal choice
Reference Books:
1. Proakis and Manolakis, “Digital Signal Processing”, Prentice Hall 1996. (Fourth Edition).
2. Roberto Cristi, “Modern Digital Signal Processing”, Cengage Publishers, India, (Erstwhile
Thompson Publications), 2003.
Sub Title : Coding Theory
Sub Code: ELD22
No. of Credits:4= 4:0:0(L-T-P)
No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
UNIT
NO.
1
2
3
4
5
SYLLABUS CONTENT
No. of
TEACHING
HOURS
Information and Entropy: Sources of information, DMS and Markov.
Properties of Entropy. Entropy of information sources, Extension of a
DMS.
10
Information channels, probability relations in a channel, A Priori, A
Posteriori Entropies, Equivocation, Mutual information, Capacity of BSC,
BEC, Noiseless and deterministic channels.
Source coding: Uniquely EL Dodable codes, Instantaneous codes and its
construction, Average length of a code, Bounds for Average
Length,Kraft'sInequality. R-ary compact codes. Code efficiency,
Redundancy. Shannon-Fano and Huffman code.
Algebra: Groups, rings and fields, properties of finite fields, Galois field
arithmetic and its realization, Vector spaces, Matrices.
Channel Coding: Block codes, Minimum distance of a block code,
Singleton bound. Performance of Codes. Hamming codes. Cyclic codes,
Golay Codes BCH codes, R-S codes. Convolutional codes. Viterbi
Algorithm. LDPC Codes.
10
11
10
11
Note: Unit numbers: 3& 4 will have internal choice
Reference Books:
1. S. Lin and D. J. Costello Jr, “Error Control Coding”, Pearson Prentice Hall, 2004
2. T. K. Moon, “Error Correction Coding: Mathematical Methods And Algorithms”, Student
Edition, John Wiley & Sons, 200
17
Sub Title : SOFT COMPUTING
Sub Code: ELD23
No. of Credits:4= 3:2:0(L-T-P)
No. of Lecture hours / week : 5Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 65
Course objectives:
1. To provide concepts of soft computing and design controllers based on ANN and Fuzzy
systems.
2. To identify systems using soft computing techniques.
3. To give an exposure to optimization using genetic algorithm.
4. To provide a knowledge on hybrid systems.
UNIT
No of Hours
NO.
SYLLABUS CONTENT
Theory
Tutorial
1
2
3
4
5
Biological foundations - ANN models - Types of activation
function - Introduction to Network architectures - Multi
Layer Feed Forward Network (MLFFN) - Radial Basis
Function Network (RBFN) - Recurring Neural Network
(RNN).
Learning process : Supervised and unsupervised learning Error-correction learning - Hebbian learning – Boltzmen
learning - Single layer and multilayer perceptrons - Least
mean square algorithm – Back propagation algorithm Applications in pattern recognition, Case studies Identification and control of linear and nonlinear systems.
Fuzzy sets: Fuzzy set operations - Properties - Membership
functions, Fuzzy to crisp conversion, fuzzification and
defuzzification methods, applications in engineering
problems.
Fuzzy control systems: Introduction - simple fuzzy logic
controllers with examples - Special forms of fuzzy logic
models, classical fuzzy control problems, inverted
pendulum, image processing, home heating system,
Adaptive fuzzy systems.
Genetic Algorithm: Introduction - basic concepts of Genetic
Algorithm, applications.
Hybrid Systems: Adaptive Neuro fuzzy Inference System
(ANF1S), Neuro –Genetic, Fuzzy-Genetic systems.
08 Hours
05 Hours
08 Hours
05 Hours
08 Hours
05 Hours
08 Hours
05 Hours
08 Hours
05 Hours
Note: Unit numbers: 2 & 5 will have internal choice
Upon successful completion of this course, students will be able to:
1. To design a complete feedback system based on ANN or Fuzzy control.
18
2. To identify systems using soft computing techniques.
3. To use genetic algorithm to find optimal solution to a given problem.
4. To design systems by judiciously choosing hybrid techniques.
Sub Title : Real Time Operating Systems
Sub Code: ELD24
No. of Credits:4= 4:0:0(L-T-P)
No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
Course objectives:
UNIT
NO.
1
2
3
4
SYLLABUS CONTENT
Introduction to Real-Time Embedded Systems: Brief history of
Real Time Systems, A brief history of Embedded Systems.
System Resources: Resource Analysis, Real-Time Service Utility,
Scheduling Classes, The Cyclic Executive, Scheduler Concepts,
Preemptive Fixed Priority Scheduling Policies, Real-Time OS, Thread
Safe Reentrant Functions.
Processing: Preemptive Fixed-Priority Policy, Feasibility, Rate
Montonicleast upper bound, Necessary and Sufficient feasibility,
Deadline –Monotonic Policy, Dynamic priority policies.
I/O Resources: Worst-case Execution time, Intermediate I/O,
Execution efficiency, I/O Architecture.
Memory: Physical hierarchy, Capacity and allocation, Shared
Memory, ECC Memory, Flash file systems.
Multi-resource Services: Blocking, Deadlock and livestock, Critical
sections to protect shared resources, priority inversion.
Soft Real-Time Services: Missed Deadlines, QoS, Alternatives to
rate monotonic policy, Mixed hard and soft real-time services.
Embedded System Components: Firmware components, RTOS
system software mechanisms, Software application components.
Debugging Components: Exceptions assert, Checking return codes,
Single-step debugging, kernel scheduler traces, Test access ports,
Trace ports, Power-On self test and diagnostics, External test
equipment, Application-level debugging.
19
No. of
TEACHING
HOURS
10
11
10
11
Performance Tuning: Basic concepts of drill-down tuning, hardware
– supported profiling and tracing, Building performance monitoring
into software, Path length, Efficiency, and Call frequency,
Fundamental optimizations.
High availability and Reliability Design: Reliability and
Availability, Similarities and differences, Reliability, Reliable
software, Available software, Design tradeoffs, Hierarchical
applications for Fail-safe design.
5
10
Note: Unit numbers: 2 & 5 will have internal choice
Reference Books:
1. Sam Siewert, “Real-Time Embedded Systems and Components”, Cengage Learning India
Edition, 2007.
2. MykePredko, “Programming and Customizing the PIC microcontroller”, 3rd Ed, TMH,
2008.
3. Dreamtech Software Team, “Programming for Embedded Systems”, Jhon Wiley, India
Pvt. Ltd., 2008.
Sub Title : ADAPTIVE SIGNAL PROCESSING
Sub Code: ELD 261
No. of Credits:4= 4:0:0(L-T-P)
No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
Course objectives
1.
2.
3.
4.
5.
Analyze adaptive system with examples.
Analyze the performance surface of Adaptive filters.
Design steepest descent algorithms and analyze the algorithm.
Design and Analyze LMS algorithm and applications.
Design Kalman filtering using different process
20
UNIT
NO.
1
2
3
4
5
SYLLABUS CONTENT
Introduction to Adaptive Systems: Adaptive Systems: Definitions,
Characteristics, Applications, Example of an Adaptive System. The
Adaptive Linear Combiner - Description, Weight Vectors, Desired
Response Performance function - Gradient & Mean Square Error
Development of Adaptive Filter Theory & Searching the
Performance surface: Introduction to Filtering - Smoothing and
Prediction – Linear Optimum Filtering, Problem statement, Principle
of Orthogonality - Minimum Mean Square Error, Wiener- Hopf
equations, Error Performance - Minimum Mean Square Error.
Searching the performance surface – Methods & Ideas of
Gradient Search methods - Gradient Searching Algorithm & its
Solution - Stability & Rate of convergence - Learning Curves.
Steepest Descent Algorithms: Gradient Search by Newton’s
Method, Method of Steepest Descent, Comparison of Learning
Curves.
LMS Algorithm & Applications: Overview - LMS Adaptation
algorithms, Stability & Performance analysis of LMS Algorithms LMS Gradient & Stochastic algorithms - Convergence of LMS
algorithm.
Applications: Noise cancellation – Cancellation of Echoes in long
distance telephone circuits, Adaptive Beam forming.
Kalman Filtering: Introduction to RLS Algorithm, Statement of
Kalman filtering problem, The Innovation Process, Estimation of
State using the Innovation Process- Expression of Kalman Gain,
Filtering Examples using Kalman filtering
Note: Unit numbers: 3& 4 will have internal choice
Course outcome:
1. Analyze adaptive system with examples.
2. Analyze the performance surface of Adaptive filters.
21
No. of
TEACHING
HOURS
12
11
10
11
8
3. Design steepest descent algorithms and analyze the algorithm.
4. Design and Analyze LMS algorithm and applications.
5. Design Kalman filtering using different process
TEXT BOOKS:
1. Adaptive Signal Processing - Bernard Widrow, Samuel D.Strearns, 2005, PE.
2. Adaptive Filter Theory - Simon Haykin-, 4th Ed., 2002, PE Asia.
REFERENCE BOOKS:
1. Optimum signal processing: An introduction - Sophocles. J. Orfamadis, 2nd Ed.,
1988, McGraw-Hill, New York
2. Adaptive signal processing-Theory and Applications - S.Thomas Alexander, 1986,
Springer –Verlag.
3. Signal analysis – Candy, Mc Graw Hill Int. Student Edition
4. James V. Candy - Signal Processing: A Modern Approach, McGraw-Hill,
International Edition, 1988.
Sub Title : MULTIMEDIA COMMUNICATION
Sub Code: ELD 262
No. of Credits:4= 4:0:0(L-T-P)
No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
UNIT
NO.
No. of
TEACHING
HOURS
SYLLABUS CONTENT
1
Multimedia
Communications:
multimedia
representation, multimedia networks, multimedia
network QoS and application QoS.
2
Information Representation: text, images, audio and video, Text and
image compression, compression principles, text compression, image
compression. Audio and video compression, audio compression, video
compression, video compression principles, video compression
standards: H.261, H.263, P1.323, MPEG 1, MPEG 2, Other coding
formats for text, speech, image and video.
22
information
applications,
10
11
3
Detailed Study of MPEG 4: coding of audiovisual objects, MPEG 4
systems, MPEG 4 audio and video, profiles and levels. MPEG 7
standardization process of multimedia content description, MPEG 21
multimedia framework, Significant features of JPEG 2000, MPEG 4
10
transport across the Internet
4
5
Synchronization:
notion
of
synchronization,
presentation
requirements, reference model for synchronization, Introduction to
SMIL, Multimedia operating systems, Resource management, process
management techniques.
11
Multimedia Communication Across Networks: Layered video
coding, error resilient video coding techniques, multimedia transport
across IP networks and relevant protocols such as RSVP, RTP, RTCP,
DVMRP, multimedia in mobile networks, multimedia in broadcast
networks
10
Note: Unit numbers: 3& 4 will have internal choice
Reference Books:
1. Fred Halsall, “Multimedia Communications”, Pearson education, 2001
2. K. R. Rao, Zoran S. Bojkovic, Dragorad A. Milovanovic, “Multimedia Communication Systems”,
Pearson education, 2004
3. Raif steinmetz, Klara Nahrstedt, “Multimedia: Computing, Communications and applications”,
Pearson education, 2002
4. Tay Vaughan, “Multimedia: Making it work”, 6th edition, Tata McGraw Hill, 2004
5. John Billamil, Louis Molina, “Multimedia: An Introduction”, PHI, 2002
6. Pallapa Venkataram, “Multimedia Information Systems”, Pearson education (In Press), 2005
23
Sub Title : ADVANCES IN IMAGE AND VIDEO PROCESSING
Sub Code: ELD 262
No. of Credits:4= 4:0:0(L-T-P)
No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
UNIT
NO.
SYLLABUS CONTENT
No. of
TEACHING
HOURS
1
Introduction: 2D systems, Mathematical preliminaries – Fourier
Transform, Z Transform, Optical &
Modulation transfer function, Matrix theory, Random signals, Discrete
Random fields, Spectral density
function.
Image Perception: Light, Luminance, Brightness, Contrast, MTF of the
visual system, Visibility function,
Monochrome vision models, Fidelity criteria, Color representation,
Chromaticity diagram, Color coordinate
systems, Color difference measures, Color vision model, Temporal
properties of vision.
10
2
Image Sampling and Quantization: Introduction, 2D sampling theory,
Limitations in sampling &
reconstruction, Quantization, Optimal quantizer, Compander, Visual
quantization.
Image Transforms: Introduction, 2D orthogonal & unitary transforms,
Properties of unitary transforms, DFT,
DCT, DST, Hadamard, Haar, Slant, KLT, SVD transform.
11
3
Image Enhancement: Point operations, Histogram modeling, spatial
operations, Transform operations, Multispectral
image enhancement, false color and Pseudo-color, Color Image
enhancement.
Image Filtering & Restoration: Image observation models, Inverse &
Wiener filtering, Fourier Domain filters,
Smoothing splines and interpolation, Least squares filters, generalized
inverse, SVD and Iterative methods,
Maximum entropy restoration, Bayesian methods, Coordinate
transformation & geometric correction, Blind
de-convolution
10
24
4
5
Image Analysis & Computer Vision: Spatial feature extraction,
Transform features, Edge detection,
Boundary Extraction, Boundary representation, Region representation,
Moment representation, Structure,
Shape features, Texture, Scene matching & detection, Image
segmentation, Classification Techniques.
Image Reconstruction from Projections: Introduction, Radon
Transform, Back projection operator,
Projection theorem, Inverse Radon transform, Fourier reconstruction, Fan
beam reconstruction, 3D
tomography.
11
Video Processing: Fundamental Concepts in Video – Types of video
signals, Analog video, Digital video,
Color models in video, Video Compression Techniques – Motion
compensation, Search for motion vectors,
H.261, H.263, MPEG I, MPEG 2, MPEG 4, MPEG 7 and beyond,
Content based video indexing.
10
Note: Unit numbers: 3& 4 will have internal choice
Text Books:
1. . K. Jain, “Fundamentals of Digital Image Processing”, Pearson Education (Asia) Pte.
Ltd./Prentice Hall of India, 2004.
2. R. C. Gonzalez and R. E. Woods, “Digital Image Processing”, 2nd edition, Pearson
Education (Asia)Pte. Ltd/Prentice Hall of India, 2004.
3. M. Tekalp, “Digital Video Processing”, Prentice Hall, USA, 1995.
REFERENCE BOOKS:
1. Z. Li and M.S. Drew, “Fundamentals of Multimedia”, Pearson Education (Asia) Pte. Ltd.,
2004.
25
Sub Title : DATA ENCRYPTION TECHNIQUES
Sub Code: ELD 262
No. of Credits:4= 4:0:0(L-T-P)
No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
UNIT
NO.
1
2
3
4
5
No. of
TEACHING
HOURS
SYLLABUS CONTENT
1. Introduction to Information Security: Introduction; What is
security? Critical characteristics of information; NSTISSC security
model; Approaches to information security implementation; The
SecuritySystem Development Life Cycle; Information Security
Terminology.
2. Planning for Security: Introduction; Information Security Policy,
Standards, and Practices; The Information Security Blue Print.
Security Technology: Firewalls and VPNs: Introduction, Physical
design, Firewalls, Protecting Remote Connections. Intrusion
Detection, Access control and Other Security Tools: Introduction;
Intrusion Detection Systems (IDS); Honey Pots, Honey Nets, and
Padded cell systems; Scanning and Analysis Tools; Access Control
Devices.
Information Security maintenance: Introduction;
Management Models; The Maintenance Model.
Security
Introduction to Network Security: Attacks, Services, and
Mechanisms; Security Attacks; Security Services; A model for
Internetwork Security; Internet Standards and RFCs; Wireless
network security.
Cryptography: Conventional Encryption Principles and Algorithms;
Cipher Block Modes of Operation;Location of encryption devices;
Key distribution; Approaches to message authentication; Secure Hash
functions and HMAC; Public Key Cryptography Principles and
Algorithms; Digital Signatures; Key management.
26
10
11
10
11
10
Note: Unit numbers: 3& 4 will have internal choice
TEXT BOOKS:
1. Michael E. Whitman and Herbert J. Mattord: Principles of Information Security, 2nd Edition,
Cengage
Learning, 2005.
2. William Stallings: Network Security Essentials Applications and Standards, Person, 2000.
3. Deven N. Shah: Information Security – Principles and Practice, Wiley India, 2009.
REFERENCE BOOK:
1. Behrouz A. Forouzan: Cryptography and Network Security, Tata McGraw-Hill, 2007.
Sub Title : Digital Electronics Lab -2
Sub Code: ELD 262
No. of Credits:4= 4:0:0(L-T-P)
No. of Lecture hours / week : 4Hrs
Exam Duration : 3 Hrs
CIE + SEE = 50 + 50=100
Total No. of contact hours : 52
Graphical Programming using LabVIEW
2. Design of 4 bit Adders (CLA, CSA, CMA, Parallel adders)
3. Design of Binary Subtractors
4. Design of Encoder (8X3), ELDoder(3X8)
5. Design of Multiplexer (8X1), and Demultiplexer (1X8)
6. Design of code converters & Comparator
7. Design of FF (SR, D, T, JK, and Master Slave with delays)
8. Design of registers using latches and flip-flops
9. Design of 8 bit Shift registers
10. Design of Asynchronous & Synchronous Counters
ARM-CORTEX M3
[Programming to be done using Keiluvision 4 and download the program on to a M3
evaluation board such as NXP LPC1768 or ATMEL ATSAM3U].
1.
2.
3.
4.
5.
6.
Write an Assembly language program to calculate 10+9+8+.........+1
Write a Assembly language program to link Multiple object files and link them together.
Write a Assembly language program to store data in RAM.
Write a C program to Output the "Hello World" message using UART.
Write a C program to Design a Stopwatch using interrupts.
Write an Exception vector table in C
27
7. Write an Assembly Language Program for locking a Mutex.
8. Write a SVC handler in C. Use the wrapper code to extract the correct stack frame
starting location. The C handler can then use this to extract the stacked PC location and
the stacked register values.
28