Florida International University
Chapter 17
Micro-programmed Control
•Molina,
•Pineiro,
•Romero,
Francisco
Michael
Rubymir
Basic Concepts

Microprogrammed Control Unit: The
logic of the control unit is specified by a
microprogram.

Microprogram: Sequence of instructions
in a microprogramming language; these
instructions are simple and specify microoperations.
Basic Concepts II
◦ Each micro-operation is described by a
symbolic notation, which looks like a
programming language (Microprogramming Language).
◦ Each line describes a set of micro-operations
(Microinstructions).
◦ A sequence of instructions is a
Microprogram, or firmware.
Implementation of Control Unit Using
the Concept of Microprogramming(1)





All the control unit is allowed to do is to
generate a set of control signals.
For each micro-operation, each micro line from
control unit is on or off.
Represent each control signal by a binary digit
(bit), or 1 and 0.
Construct a control word each bit: one
control line
Each micro-operation represented by different
patterns of 0s and 1s in the control word.
Implementation of Control Unit Using
the Concept of Microprogrmming(1I)
Place control words in memory; each word
with a unique address.
 Add address field to each control word, to
indicate location of next control word to be
executed under given conditions.
 Add a few bits to specify the condition.

Typical Microinstruction Formats
Micro-Instruction Types
◦ Vertical micro-programming

Each micro-instruction specifies single (or
few) micro-operations to be performed
◦ Horizontal micro-programming

Each micro-instruction specifies many
different micro-operations to be
performed in parallel
Horizontal Micro-programming
Wide memory word
 High degree of parallel operations
possible
 Little encoding of control information

Vertical Micro-programming
Width is narrow
 Limited ability to express parallelism
 Considerable encoding of control
information requires external memory
word decoder to identify the exact
control line being manipulated

Contains the
address of next
microinstruction
Control Unit
Loads the control
address register and
issues a read
command
Contains stored
set of
microinstructions
When a microinstruction is read from the
Control Memory, it is transferred to a Control
Buffer Register
Control Unit Function & Organization
During one clock pulse
 Sequence logic unit issues read
command to the control unit.
 Word specified in control
address register is read into
control buffer register
 Control buffer register
contents generates control
signals and next address
information for the sequencing
logic unit
 Sequence logic loads new
address into control buffer
register based on next address
information from control buffer
register and ALU flags
Advantages & Disadvantages
Simplifies the design of the control unit.
 Cheaper and less error prone for
implementation.
 The decoders and sequenced logic unit
are very simple pieces of logic in
comparison to a hardwired control unit,
which has complex logic for sequencing.
 Slower that a hardwired unit of
comparable technology.

Tasks Done By
Microprogrammed Control Unit
Microinstruction sequencing
 Microinstruction execution
 Must consider both together

Design Considerations
Size of microinstructions
 Address generation time

◦ Determined by instruction register
 Once per cycle, after instruction is fetched
◦ Next sequential address
 Common in most designed
◦ Branches
 Both conditional and unconditional
Sequencing Techniques
Based on current microinstruction,
condition flags, contents of IR, control
memory address must be generated
 Based on format of address information

◦ Two address fields
◦ Single address field
◦ Variable format
Branch Control Logic:
Two Address Fields
This is the simplest approach,
a multiplexer provides
a destination for both
address fields, and the IR.
The next two approaches
have one bit designating
which format will be used.
Branch Control
Logic: Single
Address Field
This format has the remaining
bits are used to activate the
Control Signal.
The next address is either the
next sequential address or a
derived address from the IR.
Branch Control
Logic:Variable
Format
In the second format either
the conditional or
unconditional branch is being
specified. The disadvantage is
that an entire cycle is used to
each microinstruction
Address Generation
Explicit
Implicit
Two-field
Mapping
Unconditional Branch
Addition
Conditional branch
Residual control
A conditional branch instruction depends on:
ALU flags, the Opcode or address fields of the instruction,
the register, and the status bits of the Control Unit.
MICROPROGRAMMED CONTROL
• Control Memory
• Sequencing Microinstructions
• Microprogram Example
• Design of Control Unit
• Microinstruction Format
Implementation of Control Unit
COMPARISON OF CONTROL UNIT IMPLEMENTATIONS
Control Unit Implementation
Combinational Logic Circuits (Hard-wired)
Control Data
Memory
IR
Status F/Fs
Control Unit's State
Timing State
Control
Points
Combinational
Logic Circuits
Ins. Cycle State
CPU
Microprogram
M
e
m
o
r
y
Control Data
IR
Status F/Fs
Next Address
Generation
Logic
C
S
A
R
Control
Storage
(-program
memory)
C
S
D
R
D
}
C
P
s
CPU
TERMINOLOGY
Microprogram
- Program stored in memory that generates all the control signals required
to execute the instruction set correctly
- Consists of microinstructions
Microinstruction
- Contains a control word and a sequencing word
Control Word - All the control information required for one clock cycle
Sequencing Word - Information needed to decide
the next microinstruction address
- Vocabulary to write a microprogram
Control Memory(Control Storage: CS)
- Storage in the microprogrammed control unit to store the microprogram
Writeable Control Memory(Writeable Control Storage:WCS)
- CS whose contents can be modified
-> Allows the microprogram can be changed
-> Instruction set can be changed or modified
Dynamic Microprogramming
- Computer system whose control unit is implemented with
a microprogram in WCS
- Microprogram can be changed by a systems programmer or a user
TERMINOLOGY
Sequencer (Microprogram Sequencer)
A Microprogram Control Unit that determines
the Microinstruction Address to be executed
in the next clock cycle
- In-line Sequencing
- Branch
- Conditional Branch
- Subroutine
- Loop
- Instruction OP-code mapping
Sequencing
MICROINSTRUCTION SEQUENCING
Instruction code
Mapping
logic
Status
bits
Branch
logic
MUX
select
Multiplexers
Subroutine
register
(SBR)
Control address register
(CAR)
Incrementer
Control memory (ROM)
select a status
bit
Branch address
Microoperations
Sequencing Capabilities Required in a Control Storage
- Incrementing of the control address register
- Unconditional and conditional branches
- A mapping process from the bits of the machine
instruction to an address for control memory
- A facility for subroutine call and return
Sequencing
CONDITIONAL BRANCH
Load address
Control address register
Increment
MUX
Control memory
...
Status bits
(condition)
Condition select
Micro-operations
Next address
Conditional Branch
If Condition is true, then Branch (address from
the next address field of the current microinstruction)
else Fall Through
Conditions to Test: O(overflow), N(negative),
Z(zero), C(carry), etc.
Unconditional Branch
Fixing the value of one status bit at the input of the multiplexer to 1
Sequencing
MAPPING OF INSTRUCTIONS
Direct Mapping
OP-codes of Instructions
ADD
0000
AND
0001
LDA
0010
STA
0011
BUN
0100
Mapping
Bits
10 xxxx 010
.
.
.
Address
0000
0001
0010
0011
0100
ADD Routine
AND Routine
LDA Routine
STA Routine
BUN Routine
Control
Storage
Address
10 0000 010
ADD Routine
10 0001 010
AND Routine
10 0010 010
LDA Routine
10 0011 010
STA Routine
10 0100 010
BUN Routine
Sequencing
MAPPING OF INSTRUCTIONS TO MICROROUTINES
Mapping from the OP-code of an instruction to the
address of the Microinstruction which is the starting
microinstruction of its execution microprogram
Machine
Instruction
Mapping bits
Microinstruction
address
OP-code
1 0 1 1
Address
0 x x x x 0 0
0 1 0 1 1 0 0
Mapping function implemented by ROM or PLA
OP-code
Mapping memory
(ROM or PLA)
Control address register
Control Memory
Microprogram
MICROPROGRAM
Computer Configuration
MUX
10
0
AR
Address
10
0
Memory
2048 x 16
PC
MUX
6
0
SBR
6
0
15
CAR
Control memory
128 x 20
Control unit
0
DR
Arithmetic
logic and
shift unit
15
0
AC
EXAMPLE
Microprogram
MACHINE INSTRUCTION FORMAT
Machine instruction format
15 14
11 10
Opcode
I
0
Address
Sample machine instructions
Symbol
ADD
BRANCH
STORE
EXCHANGE
OP-code
0000
0001
0010
0011
Description
AC  AC + M[EA]
if (AC < 0) then (PC  EA)
M[EA]  AC
AC  M[EA], M[EA]  AC
Microinstruction Format
3
F1
3
F2
3
F3
2
CD
2
BR
7
AD
F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
AD: Address field
EA is the effective address
Microprogram
MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3
F1
000
001
010
011
100
101
110
111
Microoperation
None
AC  AC + DR
AC  0
AC  AC + 1
AC  DR
AR  DR(0-10)
AR  PC
M[AR]  DR
F3
000
001
010
011
100
101
110
111
Symbol
NOP
ADD
CLRAC
INCAC
DRTAC
DRTAR
PCTAR
WRITE
Microoperation
None
AC  AC  DR
AC  AC’
AC  shl AC
AC  shr AC
PC  PC + 1
PC  AR
Reserved
F2
000
001
010
011
100
101
110
111
Symbol
NOP
XOR
COM
SHL
SHR
INCPC
ARTPC
Microoperation
None
AC  AC - DR
AC  AC  DR
AC  AC  DR
DR  M[AR]
DR  AC
DR  DR + 1
DR(0-10)  PC
Symbol
NOP
SUB
OR
AND
READ
ACTDR
INCDR
PCTDR
Microprogram
MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR
CD
00
01
10
11
Condition
Always = 1
DR(15)
AC(15)
AC = 0
BR
00
Symbol
JMP
01
CALL
10
11
RET
MAP
Symbol
U
I
S
Z
Comments
Unconditional branch
Indirect address bit
Sign bit of AC
Zero value in AC
Function
CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
CAR  SBR (Return from subroutine)
CAR(2-5)  DR(11-14), CAR(0,1,6)  0
Microprogram
SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language
• A symbolic microprogram can be translated into its binary equivalent
by a microprogram assembler.
Sample Format
five fields:
Label:
label; micro-ops; CD; BR; AD
may be empty or may specify a symbolic
address terminated with a colon
Micro-ops: consists of one, two, or three symbols
separated by commas
CD:
one of {U, I, S, Z}, where
U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC
BR:
one of {JMP, CALL, RET, MAP}
AD:
one of {Symbolic address, NEXT, empty}
Microprogram
SYMBOLIC MICROPROGRAM - FETCH ROUTINE
During FETCH, Read an instruction from memory
and decode the instruction and update PC
Sequence of microoperations in the fetch cycle:
AR  PC
DR  M[AR], PC  PC + 1
AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0
Symbolic microprogram for the fetch cycle:
FETCH:
ORG 64
PCTAR
READ, INCPC
DRTAR
U JMP NEXT
U JMP NEXT
U MAP
Binary equivalents translated by an assembler
Binary
address
1000000
1000001
1000010
F1
110
000
101
F2
000
100
000
F3
000
101
000
CD
00
00
00
BR
00
00
11
AD
1000001
1000010
0000000
SYMBOLIC MICROPROGRAM
Microprogram
• Control Storage: 128 20-bit words
• The first 64 words: Routines for the 16 machine instructions
• The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
• Mapping:
OP-code XXXX into 0XXXX00, the first address for the 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60
Partial Symbolic Microprogram
Label
ADD:
BRANCH:
OVER:
STORE:
EXCHANGE:
FETCH:
INDRCT:
Microops
BR
AD
I
U
U
CALL
JMP
JMP
INDRCT
NEXT
FETCH
ORG 4
NOP
NOP
NOP
ARTPC
S
U
I
U
JMP
JMP
CALL
JMP
OVER
FETCH
INDRCT
FETCH
ORG 8
NOP
ACTDR
WRITE
I
U
U
CALL
JMP
JMP
INDRCT
NEXT
FETCH
ORG 12
NOP
READ
ACTDR, DRTAC
WRITE
I
U
U
U
CALL
JMP
JMP
JMP
INDRCT
NEXT
NEXT
FETCH
ORG 64
PCTAR
READ, INCPC
DRTAR
READ
DRTAR
U
U
U
U
U
JMP
JMP
MAP
JMP
RET
NEXT
NEXT
ORG 0
NOP
READ
ADD
CD
NEXT
Microprogram
BINARY MICROPROGRAM
Micro Routine
ADD
BRANCH
STORE
EXCHANGE
FETCH
INDRCT
Address
Decimal Binary
0
0000000
1
0000001
2
0000010
3
0000011
4
0000100
5
0000101
6
0000110
7
0000111
8
0001000
9
0001001
10
0001010
11
0001011
12
0001100
13
0001101
14
0001110
15
0001111
64
65
66
67
68
1000000
1000001
1000010
1000011
1000100
F1
000
000
001
000
000
000
000
000
000
000
111
000
000
001
100
111
Binary Microinstruction
F2
F3
CD
000
000
01
100
000
00
000
000
00
000
000
00
000
000
10
000
000
00
000
000
01
000
110
00
000
000
01
101
000
00
000
000
00
000
000
00
000
000
01
000
000
00
101
000
00
000
000
00
BR
01
00
00
00
00
00
01
00
01
00
00
00
01
00
00
00
AD
1000011
0000010
1000000
1000000
0000110
1000000
1000011
1000000
1000011
0001010
1000000
1000000
1000011
0001110
0001111
1000000
110
000
101
000
101
000
100
000
100
000
00
00
11
00
10
1000001
1000010
0000000
1000100
0000000
000
101
000
000
000
This microprogram can be implemented using ROM
00
00
00
00
00
Design of Control Unit
DESIGN OF CONTROL UNIT
- DECODING ALU CONTROL INFORMATION microoperation fields
F1
F2
F3
3 x 8 decoder
3 x 8 decoder
3 x 8 decoder
7 6 54 3 21 0
7 6 54 3 21 0
76 54 3 21 0
AND
ADD
Arithmetic
logic and
shift unit
DRTAR
PCTAR
DRTAC
From
From
PC DR(0-10)
Select
Load
Load
AC
DR
AC
0
1
Multiplexers
AR
Clock
Microinstruction Format
HORIZONTAL AND VERTICAL
MICROINSTRUCTION FORMAT
Horizontal Microinstructions
Each bit directly controls each micro-operation or each control point
Horizontal implies a long microinstruction word
Advantages: Can control a variety of components operating in parallel.
--> Advantage of efficient hardware utilization
Disadvantages: Control word bits are not fully utilized
--> CS becomes large --> Costly
Vertical Microinstructions
A microinstruction format that is not horizontal
Vertical implies a short microinstruction word
Encoded Microinstruction fields
--> Needs decoding circuits for one or two levels of decoding
Two-level decoding
One-level decoding
Field A
2 bits
2x4
Decoder
1 of 4
Field B
3 bits
3x8
Decoder
1 of 8
Field A
2 bits
2x4
Decoder
Field B
6 bits
6 x 64
Decoder
Decoder and
selection logic
Review Questions
10.
What is the difference between a hardwired implementation and a microprogrammed implementation of a control unit?
How is a horizontal microinstruction interpreted?
What is the purpose of the control memory?
What is the typical sequence in the execution of a horizontal microinstruction?
What is the difference between horizontal and vertical microinstruction?
What is the difference between functional and resource encoding?
List some common applications of microprogramming.
Where is the opcode in the address ?
What is the formula to calculate the number of bit need for a given number of
signal controls?
Where is the microinstruction code store ?
11.
http://en.wikipedia.org/wiki/Firmware
1.
2.
3.
4.
5.
6.
7.
8.
9.