Lecture 2
State-of-the art of CMOS Technology
1
The CMOS Transistor
2
The NMOS Transistor Cross Section
Polysilicon
W
Gate
Source
n+
Gate oxide
Drain
n+
L
p substrate
Bulk (Body)
Field-Oxide
(SiO2)
Self-Aligned Gates NMOS Process
1. Create thin oxide in the
“active” regions, thick
elsewhere
2. Deposit polysilicon
3. Etch thin oxide from
active region (poly acts
as a mask for the
diffusion)
4. Implant dopant
4
Photo-Lithographic Process
optical
mask
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
5
spin, rinse, dry
Patterning - Photolithography
1. Oxidation SiO2
deposits a thin layer of SiO2 over the
complete wafer
•
Wet Oxidation: water vapor
(Furnace 900°C, 15 min, 40 nm)
Si + 2H2O
•
 SiO2 + 2H2
Dry oxidation: Pure O2
(Furnace 1000°C, 45 min, 40 nm)
Si + O2
•
6
 SiO2
insulation layer and also forms
transistor gates.
SiO2
Patterning - Photolithography
2. Photoresist coating:
•
a light-sensitive polymer is evenly
applied while spinning the wafer to
a thickness of approximately 1 µm.
•
SiO2
-ve Photoresist:
Originally soluble in organic solvent,
but insoluble after exposure to UV
light.
•
7
+ve Photoresist:
Originally insoluble in organic
solvent, but soluble after exposure
to UV light.
PR
Patterning - Photolithography
3. Stepper exposure:
•
•
•
a glass mask , containing the
patterns that we want to transfer
to the silicon
opaque in the regions that we
want to process, transparent in
the others (assuming a negative
Photoresist)
Where the mask is transparent,
mask
the Photoresist becomes
insoluble.
SiO2
8
UV light
PR
Patterning - Photolithography
4. Photoresist development
and bake:
•
•
9
the wafers are developed in either an
acid or base solution to remove the
non-exposed areas of Photoresist.
wafer is “soft-baked” (after PR
removal) at a low temperature to
harden the remaining Photoresist.
Patterning - Photolithography
5. Acid etching:
•
material is selectively removed from
areas of the wafer that are not
covered by Photoresist.
•
accomplished through the use of many
different types of acid, base and caustic
solutions as a function of the material that
is to be removed.
10
Patterning - Photolithography
6. Spin, rinse, and dry:
•
•
•
•
•
11
a special tool (called SRD) cleans the
wafer with deionized water and dries it
with nitrogen.
smallest particle of dust or dirt can
destroy the circuitry.
processing steps are performed in ultraclean rooms where the number of dust
particles per cubic foot of air ranges
between 1 and 10.
the wafers must be constantly cleaned to
avoid contamination, and to remove the
left-over of the previous process steps.
Patterning - Photolithography
7. Various Process step:
the exposed area can
now be subjected to a
wide range of process
steps
 Diffusion or Ion implantation
 Plasma etching
 Metal deposition
12
Patterning - Photolithography
6. Photoresist Removal
(ashing):
• a high-temperature plasma (
mix of chemical materials) is
used to selectively remove
the remaining Photoresist
without damaging device
layers.
13
Example: Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
Si-substrate
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Hardened resist
SiO
2
(b) After oxidation and deposition
of negative photoresist
Si-substrate
UV-light
Patterned
optical mask
(e) After etching
Exposed resist
Si-substrate
(c) Stepper exposure
14
SiO
2
Si-substrate
(f) Final result after removal of resist
Process steps
1)
Diffusion or Ion implantation:
Diffusion implantation:
•
•
•
•
15
the wafers are placed in a quartz
tube embedded in a heated furnace.
A gas containing the dopant is
introduced in the tube.
The high temperatures of the
furnace, typically 900 to 1100 °C,
cause the dopants to diffuse into the
exposed surface both vertically and
horizontally.
Not accurate (difference in dopant
concentration through the material)
Process steps
1)
Diffusion or Ion implantation:
Ion implantation:
•
•
•
•
•
16
dopants are introduced as ions into
the material.
The ion implantation system directs
and sweeps a beam of purified ions
over the semiconductor surface.
The acceleration of the ions
determines how deep they will
penetrate the material,
the beam current and the exposure
time determine the dosage.
It controls depth and dosage,
therefore it displaced diffusion
implantation in modern
semiconductor manufacturing.
Process steps
2) Deposition:
•
Oxidation SiO2 (insulating material)

CVD (Chemical Vapor Deposition) of
(Si3N4)
(buffer layer, to protect the field oxide )

chemical deposition (polysilicon)
(flows silane gas over the heated wafer
coated with SiO2 at a temperature of
approximately 650°C

sputtering (Al)
(The aluminum is evaporated in a vacuum,
with the heat for the evaporation delivered
by electron-beam or ion-beam bombarding.
)
17
Process steps
3) Etching:
etching is used to selectively form patterns such as Via and contact holes.
•
Wet Etching:
(makes use of acid or basic solutions, such as hydrofluoric acid to etch SiO2)
•
Dry (or Plasma) Etching:
- A wafer is placed into the etch tool's processing chamber and given a negative
electrical charge.
- The chamber is heated to 100°C and brought to a vacuum level of 7.5 Pa, then
filled with a positively charged plasma (usually a mix of nitrogen, chlorine and
boron trichloride).
- The opposing electrical charges cause the rapidly moving plasma molecules to
align themselves in a vertical direction, forming a microscopic chemical and
physical “sandblasting” action which removes the exposed material.
- Plasma etching has the advantage of offering a well-defined directionality to the
etching action, creating patterns with sharp vertical contours.
18
Process steps
4) Planarization:
•
This process uses a slurry compound—a liquid
carrier with a suspended abrasive component
such as aluminum oxide or silica—to
microscopically plane a device layer and to
reduce the step heights.
•
chemical-mechanical planarization (CMP) step is
included before the deposition of an extra metal
layer on top of the insulating SiO2 layer.
19
CMOS Process
20
CMOS Process Layers Color Legend
Layer
Color
Well (n)
Green
Active Area (n+)
Green
Select (n+)
Green
Well (p)
Active Area (p+)
Yellow
Yellow
Select (p+)
Yellow
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact or Via
21
Black
Representation
Complete Simplified CMOS Inverter Process
cut line
VDD
M2
In
Out
M1
p well
22
P-Well Mask Creation in the N Type Substrate
23
Active Mask Creation (n+ and p+ Regions) (Continue)
24
Poly Silicon Mask Creation
25
P+ Mask Creation
26
N+ Mask Creation (Continue)
27
Contact Mask Creation
28
Metal Mask Creation (Continue)
29
A Modern CMOS Process
Twin-Tub or Dual-Well Trench
gate-oxide
TiSi2
AlCu
SiO2
Tungsten
p-well
n+
p-epi
p+
p+
Dual-Well Trench-Isolated CMOS Process
30
SiO2
n-well
Procedure of Modern CMOS Process
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers
31
•
One full photolithography
sequence per layer
(mask)
Modern CMOS Process Walk-Through
Base material: p+ substrate
with p-epi layer
p-epi
p+
SiN
34
p-epi
p+
p+
32
SiO
2
After deposition of gate-oxide
and sacrifical nitride (acts as a
buffer layer)
After plasma etch of insulating
trenches using the inverse of
the active area mask
CMOS Process Walk-Through (continue)
SiO After trench filling, CMP
2
planarization, and
removal of sacrificial
nitride
Vt  V fb  2 f 
n
p
33
2 s qN A (2 f )
C ox
qQim

C ox
After n-well and VTp
adjust implants
After p-well and VTn adjust
implants
3.5 CMOS Process Walk-Through (continue)
poly(silicon)
After polysilicon deposition
and etch
n+
p+
After n+ source/drain and
p+ source/drain implants.
These steps also dope the
polysilicon.
SiO
2
After deposition of SiO2
insulator and contact
hole etch
34
CMOS Process Walk-Through (continue)
Al
After deposition and
patterning of first Al
layer.
Al
SiO
2
After deposition of SiO2
insulator, etching of via’s,
deposition and patterning
of second layer of Al.
35
Bonding Techniques
Wire Bonding
Substrate
Die
Pad
Lead Frame
36
Tape-Automated Bonding (TAB)
Sprocket
hole
Film + Pattern
Solder Bump
Die
Test
pads
Lead
frame
Substrate
(b) Die attachment using solder bumps.
Polymer film
(a) Polymer Tape with imprinted
wiring pattern.
37
Flip-Chip Bonding
Die
Solder bumps
Interconnect
layers
Substrate
38
Package-to-Board Interconnect
(a) Through-Hole Mounting
39
(b) Surface Mount