CS-EE 481
Project Yew
Inline Power Monitor with Cost Analysis
Team
Zubin Bagai
Jon Worley
Kevin Eldrige
Founder’s Day
Faculty Advisors
Dr. Albright, Dr. Osterberg
Industry Representative
Mr. John Haner
Bonneville Power Administration
University of Portland
School of Engineering
1
CS-EE 481
Agenda
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•
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Introduction
Background
Research/Design
Results
Conclusions
Demonstration
Founder’s Day
University of Portland
Jon Worley
Kevin Eldrige
Zubin Bagai
Jon Worley
Kevin Eldrige
Team Yew
School of Engineering
2
CS-EE 481
Introduction
• The Problem:
– The U.S. is a top consumer of energy
– The typical household uses appliances when it
is convenient to do so
– Lack of knowledge about which appliances use
the most energy, inefficient
Founder’s Day
University of Portland
School of Engineering
3
CS-EE 481
Introduction (Cont’d)
• The Solution:
– In-line Power Monitor with Cost Analysis
Founder’s Day
University of Portland
School of Engineering
4
CS-EE 481
Background
• The Goal: Relate W to $
- Monitor the power usage of a household appliance
- Utilize a keypad and LCD to make the monitor
fully interactive with the user
- Provide education about device efficiency, costs
associated with time-of-use
- Project model: Sense  Process Actuate
Founder’s Day
University of Portland
School of Engineering
5
CS-EE 481
Background (Cont’d)
• Power Sensing
Prototype
- Measurements of
voltage and current
- Safety in design
- Use components that
are low power
Founder’s Day
AC
University of Portland
Power
Sensing
User
Input
Data
Processing
School of Engineering
Device
Actuate
Display
Display
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CS-EE 481
Background (Cont’d)
• Data Processing:
- Analog-to-Digital signal conversion (PIC)
- Needs to handle keypad input & LCD output (PIC)
- MOSIS capabilities (What functions can we design?)
Founder’s Day
University of Portland
School of Engineering
7
CS-EE 481
Research
• Desired functionality of the project
– Monitor Power
– LCD display (small)
– Ability to switch power on/off
• How do we produce this functionality
• Feasible?
• What will we be able to do with the MOSIS
• Result of research
– Power Sensing
– Data Processing
– User Input
Founder’s Day
University of Portland
School of Engineering
8
CS-EE 481
Design
• Integration of all parts into
a single unit
Founder’s Day
University of Portland
School of Engineering
9
CS-EE 481
Design (Cont’d)
• Power Sensing
– Measures voltage
drop and current
draw of device
– Translates these
values into small
voltages
‒ Small voltages sent
into Opto-Isolators
Founder’s Day
University of Portland
School of Engineering
10
Design (Cont’d)
CS-EE 481
• Data Processing
– PIC
Calculates power, takes keypad info to calculate cost, outputs to
LCD, sends power prices to the MOSIS chip
– MOSIS
– Determines whether the threshold price is exceeded, controls the SS
relay, keeps track of time
– Solid State Relay
Receives signal from MOSIS to allow/block power to device
Founder’s Day
University of Portland
School of Engineering
11
Design (Cont’d)
CS-EE 481
PIC
MOSIS
8 bit Present Price
A
8 bit Max Price
B
A<B
8 Bit
Comparator
A=B
1 bit Reset
Reset
A>B
1 bit Clock
7 bit Minutes
5 bit Hours
text
Reset
Clock
24 Hour Counter
Relay
Minutes
Hours
3 bit Relay Control
Founder’s Day
University of Portland
School of Engineering
12
CS-EE 481
Founder’s Day
Results
University of Portland
School of Engineering
13
CS-EE 481
Results (Cont’d)
• B2Logic Schematic
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University of Portland
School of Engineering
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CS-EE 481
Results (Cont’d)
• LEDIT Layout
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University of Portland
School of Engineering
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CS-EE 481
System Results
Individual
√ Power Sensing
√ ADC
√ Solid State Relay
√ MOSIS
√ LCD
√ Key-Pad
System
√ Power Sensing
√ ADC
√ Solid State Relay
√ MOSIS
√ LCD
√ Key-Pad
√ Power Calculation
Founder’s Day
University of Portland
School of Engineering
16
System Results
CS-EE 481
Theoretical
VLine =1001* ((VV-ADC-*19.5mV) -Vref/2)*(0.512/Vref)
ILine =(1/0.015)* ((VI-ADC*19.5mV) -Vref/2)*(0.512/Vref)
Calibration
VRMS= KV(VADC – VZero)
IRMS = KI(IADC – Izero)
Calculation
Power (W) = VRMS*IRMS
Cost = (¢/W-M) * Power
4.23 %Error
Result
Maximum Error
Founder’s Day
1¢/kW-H
University of Portland
School of Engineering
17
CS-EE 481
Conclusion
• In-line Power Monitor with Cost Analysis
– Goal: Educate, initiate change in energy-use habits
• Enhancements:
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Expand power factor table
10 bit ADC
Current sensing resistor network
Auto-calibration function in PIC
Wireless/Ethernet connectivity
Software to track energy consumption
Founder’s Day
University of Portland
School of Engineering
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CS-EE 481
Demonstration
Simulation of In-line Power Monitor with Cost Analysis
Founder’s Day
University of Portland
School of Engineering
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CS-EE 481
Special Thanks
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Dr. Robert Albright
Dr. Peter Osterberg
Dr. Joe Hoffbeck
Dr. Wayne Lu
Mr. John Haner
Mr. Craig Henry
Mr. Steve Westdal
Grant from the MOSIS Educational Program (MEP)
Founder’s Day
University of Portland
School of Engineering
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CS-EE 481
Thank You.
Are there any questions?
Founder’s Day
University of Portland
School of Engineering
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