FORMAL DESCRIPTION OF TEST SPECIFICATION AND ATE
ARCHITECTURE FOR MIXED-SIGNAL TEST
Baolin Deng, Wolfram Glauert
University of Erlangen-Nuremberg,
Institute for Computer Aided Circuit Design
Paul-Gordan-Str.5, 91052 Erlangen, Germany
[email protected], [email protected]
Abstract
This paper proposes an approach to the formal description
of test specifications and automatic test equipment (ATE) architectures for mixed-signal test. For this purpose, two sets
of standard components are defined. A test specification and
an ATE can then be described using these components and
their properties. In the end, they can be represented by several mathematical matrices. Such a description, because of
its clarity, is suitable for analysis using mathematical methods and, therefore, forms a basis for the automatic generation of an optimal test concept, which is now a particularly
weak spot for the test program and device interface board
development.
1 Introduction
The preparation of the device interface board (DIB) and the
test program for mixed-signal integrated circuit (IC) testing
is an expensive and time-consuming process, and is therefore often one of the main bottlenecks in a product development cycle. In this connection, reducing the cost and the
time to market necessitates the automatic generation of the
DIB and the test program which lead to the shortest testing
time per unit later during testing.
The automatic generation of the test program (sometimes
mentioned under the name of design test integration or virtual test) for mixed-signal test is a hot topic. The previous
efforts usually concentrated on the creation of environments
to facilitate test concept capture, test code generation and
test code simulation. DANTES [1] and TOPS-A [2] were
two well-known examples of these efforts. They improved
the development, however, only in the way that a test engineer is enabled to capture a concept quickly and to modify
it in a more efficient way if required. This is, however, not
a true automation because the concept has to be developed
by the test engineer himself. Consequently, the concept developed largely depends on the intuition and expertise of the
test engineer. It is difficult to guarantee that this concept is
error-free. It is more difficult to guarantee that the utiliza-
tion of the hardware resources is optimized, which affects
the testing time. It is clear that, based on such a hand-written
concept, it is difficult to generate a test code that is error-free
and optimal (with respect to the testing time). As a result,
significant debugging effort is still required.
Virtual test [3] is an approach to debugging the test code
in a simulation environment. Its advantage is that it enables
the debugging without the device under test (DUT) as well
as the ATE hardware, thus reducing the cost and the time
to market. Its use, however, is limited by the availability
of adequate simulators and adequate models for the DUT,
the DIB and the ATE. As a result, it is impossible to use
virtual test for an accurate verification of the whole DUTDIB-ATE system within a reasonable time. For this reason,
the acceptance of the virtual test in industry has been rather
limited [4].
DIB development has recently become a hot topic. There
are many papers dealing with design techniques (e.g. [5]),
simulation environments (e.g. [6]) and the project management (e.g. [7]). In fact, for a concrete application, a successful DIB can only result from a clear design specification.
How to generate such a specification is very important as
well. This aspect, however, has been very seldom addressed
up to now.
In summary, as stated in ITRS [8], the DIB and test program development still remains one of the most difficult
challenges in a product development cycle. To automatically generate a DIB and a test program that result in the
shortest testing time, it is the first priority to automatically
generate an optimal concept for the test code generation and
the DIB development.
The paper is organized as follows. Section 2 gives an
overview on our whole strategy of automatically generating an optimal concept. Sections 3, 4 and 5 deal with our
approach to the description of test specifications and ATE
architectures, which is central to our strategy. Among these,
Section 3 gives an overview on the approach; Sections 4 and
5 describe the approach in detail. Section 6 shows the actual
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Paper 38.1
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results. Section 7 discusses some issues associated with the
strategy. Section 8 concludes the paper.
2 Strategy
The key of our strategy is to find an approach capable of
describing the generation of an optimal test concept mathematically. We assume that if we can describe it this way we
can also automate the generation.
The generation of a test concept is shown in Fig.1. Test
specification refers to the test requirements of a DUT. ATE
architecture refers to the entirety of the resources of an ATE
including their specifications and limitations. A test concept
comprises a test program specification and a DIB specification which, as their names imply, serve as the specification
for the test code generation and the DIB development, respectively. Test conception is a process that produces a test
concept from the test specification and the ATE architecture.
Test Specification
ATE Architecture
Test Conception
Test Concept
Testprogram
Specification
DIB Specification
Fig. 1: Generation of a test concept
In order to describe the generation of a test concept, we
need to describe (1) the test specification and ATE architecture, (2) the test program specification and DIB specification, and (3) the algorithms for test conception.
An optimal test concept is a concept that can optimally
utilize the resources of the available ATE for the given test
specification, thus resulting in the shortest testing time. In
this connection, the generation of an optimal test concept
means using an optimal algorithm for test conception.
Our vision is as follows: based on these descriptions,
a tool can be developed, using which, once a specific test
specification is available, a corresponding test concept can
be generated immediately; the test concept generated is
error-free; it utilizes the ATE resources for all tests specified by the given test specification optimally.
Furthermore, due to the fact that the test program specification produced this way is also described mathematically,
optimizing mapping approaches for the test code generation
can be used. In this way, possible errors contained in the
generated test code can be reduced. The same applies to the
DIB development.
It can be expected that the resulting DIB and test program
is already functional with respect to the whole DUT-DIBATE-system without logical errors and that only a small
Paper 38.1
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amount of bugs still exist. Therefore, it is possible to isolate the critical parts of the ATE, the DIB and the DUT from
the whole system for accurate verification using the virtual
test, for which commercial simulators are available. So, the
virtual test will eventually become attractive to industry.
From the discussion above we see that the description of
the test specification and ATE architecture is the basis for
our strategy. So, the next three sections deal with this issue.
3 Approach
3.1 Problem Statement
In practice, data sheet [9, 10], test plan [9] and simulation
file [10] are used as test specification. As a data sheet and
a test plan are written in plain text, such a test specification
is inadequate for the automation and optimization. Another
possibility is a file written in STIL (IEEE Std 1450) [11],
TSDL [12], ATLAS (IEEE Std 716, IEEE Std 771) [13],
TeRM (IEEE P1598) [14] or in other general description
languages. Such a test specification is also inadequate because the test content is only implicitly defined in the file.
To obtain it, an extraction is needed. Therefore, for the automation and optimization, we need a way that describes
the test specification at a level between the documentation
written in plain text and the files represented in general description languages.
As for the description of the ATE architecture, just like
the test specification, documents such as operating manuals
(on-line or off-line) and instrument panels (on-line) as well
as files written in any description languages are also inadequate for the automation and optimization. We need a way
of description, which corresponds to that for the description
of the test specification. Compared to the test specification,
the description of an ATE architecture is particularly critical.
Typically, ATE has an irregular, historically or evolutionally
grown architecture. Modern ATE may also have to use existing structures or instruments of various concepts because
of time, cost or technical reasons. In publications associated
with the virtual test only some typical instruments have been
addressed. In addition, today only coarse models are available for the virtual test environment. Therefore, the problem
of accurate description of an ATE architecture has not been
properly formulated yet.
3.2 Formulation of a Test Specification
To develop a DIB and a test program, the following information should be given:
1. What components or circuits should be connected to
what pins of a DUT? What signals should be applied
to/observed from what pins of the DUT?
2. What parameters should be directly measured? What
calculations should be done?
Item 1 is to provide a defined condition so that the DUT
assumes a specific ”state”. So, we can use ”states” to de-
scribe the components or circuits to be connected and the
signals to be applied or observed. We distinguish between
pin state, DUT state and basic state. A pin state means a
state at a pin, and a DUT state means a state at all pins. A
basic state is used as a standard component to represent a
pin state and a DUT state. To describe them in detail, two
properties will be assigned to a basic state. The properties
for a pin state and a DUT state will be represented by the
properties of the basic states.
Item 2 is to describe any ”actions” that occur in a specific DUT state. First, we distinguish between a measurement parameter and a test parameter. The former refers
to a parameter that is contained in a signal related to a pin
of the DUT. The latter is a parameter specified in a test requirements document. Then we assume that a measurement
parameter is determined by a measurement using an instrument of an ATE. A test parameter will be determined by a
calculation from the measurement parameters. The formulas or an algorithm to calculate a test parameter is called a
test function. An action can then be defined as several measurements and one calculation.
serves to transmit signals. A cINST typically is a transmission line system, multiplexer, demultiplexer, matrix, bus as
well a hard-wired network.
Second, we consider a set of so-called basic functions to
be standard components to represent the functions of an instrument (both fINST and cINST). Each basic function will
be defined to have certain properties. The properties describe the technical data, the ports, the commands for programming and other information. Both the set of basic functions and their properties will be standardized. For each basic function, an instrument may have several so-called basic modules. All basic modules performing the same basic
function have the same type of the properties. An instrument
(both fINST and cINST) can then be described by a set of
basic modules and the corresponding properties.
Finally, we introduce the so-called signal paths for each
basic module of a fINST. A signal path means a possibility to transmit a signal from the ”original” port of the basic module to its port at the ATE interface-to-DUT or vice
versa. As the signal transmission is performed by cINSTs,
it is clear that a signal path is a chain of basic modules of
cINSTs.
Basic modules of cINSTs
Basic states and
their properties
Pin State
Pin Properties
A DUT State
T signalPath T signalPath T signalPathni j 1
Measurement
Parameter
Test
Function
Test
Parameter
ni j 11
A basic
module of
fINSTs
A test process can then be viewed as a sequence of the
DUT states and the corresponding actions. A test specification can be represented by a set of the DUT states and the
corresponding actions. Fig.2 shows this scheme.
3.3 Formulation of an ATE Architecture
To develop a DIB and a test program, the following information is necessary:
1.
2.
3.
4.
5.
6.
What functions does the ATE have?
How many modules are available for one function?
What are the technical data of each module?
What commands can be used for its programming?
What are its ports at the ATE interface-to-DUT?
How can a signal be transmitted from each module to
the ATE interface-to-DUT or vice versa?
7. What modules can be used simultaneously?
First, we distinguish between functional instrument
(fINST) and connection instrument (cINST). A fINST is an
instrument that generates signals or/and records signals (and
takes some measurements if necessary). It involves all types
of sources and meters. A cINST is an instrument that simply
Tni j 1B
Tni j aB
ni j a
An Action
Fig. 2: Scheme for formulation of a test specification
Tni j 1b
Mni j
ni j a1
ni j A
ni j A1
Tni j ab
Tni j Ab
Tni j AB
Fig. 3: Scheme for formulation of an ATE architecture
So far, we can now model an ATE as a set of basic modules of fINSTs and their signal paths consisting of basic
modules of cINSTs (Fig. 3).
4 Test Specification
4.1 Definition of a Set of Basic States
A basic state is defined as a combination of the following
items: (1) the type of a pin variation; (2) a basic component,
circuit or signal; (3) the purpose (connection, stimulation or
acquisition).
A pin variation means an arrangement of DUT pins.
There are four types of such arrangements that are usually
used (Fig.4):
(a) Two pins for one component, circuit or signal
(b) Three pins for two signals (one pin is common)
Paper 38.1
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(c) Four pins for two separate signals
(d) Four pads for one signal (Kelvin connection)
H
H1
H2
f v i v t i t v1 t v2 t i1 t i2 t L
(a) Pin−Pin
HF
HS
H1
L1
v1 t v2 t i1 t i2 t Table 2: Groups of basic states
v t
LF
H2
LS
L
L2
(b) Pin−Pin−Pin (c) Pin-Pin ( 2) (d) Pin−Pin (FS)
Fig. 4: Types of a pin variation
A basic component/circuit means a component (e.g., resistor, capacitor) or a circuit (e.g., pull-up, pull-down) to be
connected to the DUT pins (one pin variation). Open and
short are two special cases. A basic signal is a signal to be
applied to or observed from the DUT pins (one pin variation). The usually used basic signals are listed in Table 1.
Table 1: Basic signals
Signal
Note
DC
RECTp
TRIp
RAMPp
SINp
AWp
RECTnp
TRInp
RAMPnp
SINnp
AWnp
Clock
Pattern
DC
Rectangular, periodic
Triangular, periodic
Ramp, periodic
SIN, periodic
Arbitrary-Waveform, periodic
Rectangular, non-periodic
Triangular, non-periodic
Ramp, non-periodic
SIN, non-periodic
Arbitrary-Waveform, non-periodic
Clock
Pattern
Paper 38.1
1084
Pin-Pin
Pin-Pin
Pin-Pin
Pin-Pin
Pin-Pin
Pin-Pin-Pin
Pin-Pin-Pin
Pin-Pin ( 2)
Pin-Pin ( 2)
Pin-Pin (FS)
Connection
Stimulation
Stimulation
Acquisition
Acquisition
Acquisition
Acquisition
Acquisition
Acquisition
Stimulation
v2 t i2 t v2 t i2 t If ΓPi , the number of BDPs of si , is smaller than ΓP , ΓP ΓPi
symbols φ should be inserted, so that each Pi has the same
dimension. The same applies to Qi . φ denotes ”don’t care”.
s1 si sI T
(3)
T
P1 Pi PI T
Q1 Qi QI (2)
sv1 SV
PV
QV 1
QV 2
(4)
(5)
svi svI T
(6)
T
PV 1 PV i PV I T
QV 11 QV 1i QV 1I (7)
(8)
QV 21 QV 2i QV 2I T
(9)
The following definitions hold:
svi
qiγ qiΓQ T
qi1 f v i v t i t v t i t v1 t i1 t v1 t i1 t v t Obviously, a pin state and its properties can then be described using values of S, P and Q. Let SV be the value for
S and PV for P. Contrary to P, two types of values, namely
QV 1 and QV 2, will be assigned to Q. QV 1 is a binary vector
to indicate which BMPs should be measured. QV 2 is a decimal vector to store the measurement results of the BMPs.
(1)
G1
G 2V
G 2I
G 3V
G 3I
G 4V
G 4I
G 5V
G 5I
G 6V
P
Q
pi1 piγ piΓP T
Qi
Purpose
S
To describe a basic state in detail, two properties, namely
basic description parameter (BDP) and basic measurement
parameter (BMP), are introduced. A BDP is a parameter
that characterises a basic state, and a BMP is a parameter
that is attached to a basic state and may have to be measured.
Suppose si is a basic state. Let piγ and qiγ be one of its
BDPs and BMPs, respectively. All BDPs and BMPs associated with si can then be represented by a ΓP dimensional
vector Pi and a ΓQ dimensional vector Qi , respectively.
Type of a
Pin Variation
All basic states si i 1 I as well as their BDPs
1 I and their BMPs Qi i 1 I can be
Pi i arranged in a vector (S) or matrix (P and Q), respectively.
4.2 Definition of Properties for a Basic State
Basic Component,
Circuit or Signal(s)
4.3 Representation of a Pin State and its Properties
Table 2 shows 6 groups of basic states. f v i denotes
a basic component or circuit. v t , v1 t and v2 t denote
a basic voltage signal. i t , i1 t and i2 t denote a basic
current signal. G 2V , G 2I and G 6V mean the stimulation
with one basic signal. G 3V , G 3I, G 4V , G 4I, G 5V and G 5I
mean the acquisition of one or two basic signals.
Pi
Group
1
0
PV i
if si exists;
if si does not exist.
Value of Pi ΓP
φ
if svi
if svi
1;
0
QV 1i
qv1i1 qv1iγ qv1iΓQ T
QV 2i
qv2i1 qv2iγ qv2iΓQ T
qv1iγ
1
0
φ
qv2iγ
if svi
if svi
if svi
1, qiγ is to be measured;
1, qiγ is not to be measured;
0
Measurement result of qiγ φ
if qv1iγ
if qv1iγ
1;
1
k
1
2
3
4
4.4 Representation of a DUT State and its Properties
Suppose SV m k , PV m k , QV 1 m k and QV 2 m k are
SV , PV , QV 1 and QV 2 that refer to a test step with index m
and a pin variation with index k, respectively. The SV , PV ,
QV 1 and QV 2 for all pin variations in the test step m can
then be represented by the following matrices:
SV T S m PV
TS
QV 1T S m QV 2
TS
(10)
PV m K T
(11)
QV 1 m 1 QV 1 m k QV 1 m K T
(12)
QV 2 m 1 QV 2 m k QV 2 m K T
(13)
m m SV m 1 SV m k SV m K T
PV m 1 PV m k where K is the number of pin variations of the DUT.
4.5 Representation of an Action
Suppose y m u is a test parameter in the test step m, and
λ m u is the algorithm needed for calculating y m u . All
the test parameters and their algorithms in the test step m
can be represented by two U dimensional vectors Y T S m and ΛT S m :
Y T S m
ΛT S m y
m 1
λ m 1
y m u y m U T (14)
T
(15)
λ m u λ m U If Um , the number of the test parameters to be tested in the
test step m, is smaller than U, U Um symbols φ should
be inserted, so that each Y T S m and ΛT S m have always
the same dimension. Here, ΛT S m and λ m u are only a
notation. By these we mean:
ΛT S m : Y T S m λ m u : y m u
ΛT S m PV T S m QV 2T S m λ m u PV T S m QV 2T S m Table 3: A set of basic states and their properties
Basic State
s4 :=
S
Properties
Pull-down
via R to Ground
Stimulation with
v t V0
Stimulation with
v t V0 sin2πF t t0 Observation of
v t V0 sin2πF t t0 s3 :=
s1
s2
s3
s4
4
2 IN
GND
3
Last, take the test requirements listed in Table 4 (They
have been formulated in the way presented in Section 3.2).
Table 4: Test requirement for test step m
Test Parameter: A10k (the frequency response at 10kHz)
k 1 Power supply with 15V
k 2 Stimulation with v1 t A1 cos 2π10kt V
k 3 Observation of v2 t A2 cos 2π10k t t0 V ,
Pull-down via R 1kΩ
k 4 None
Measurement parameter: A2 in v2 t for k 3
Test function: A10k A2 A1 (A1 2V )
The pin states can then be represented by
SV m 1 0 1
0 0
SV m 2 0 0
1 0
SV m 3 1 0
0 1
SV m 4 0 0
0 0
Due to space limitation, we will just give the properties for
k 2 and k 3. For the meaning of ”Actual”, ”Min” and
”Max” see Table 5.
Table 5: Structures of PV m k and QV 2 m k First, let us define a set of basic states and their properties
(Table 3). To keep the dimension of matrices small, we
choose I 4 and ΓP ΓQ 4.
s2 :=
OUT
Fig. 5: DUT and its pin variations
4.6 An Example
s1 :=
1 VS
Meaning
VS−GND
IN−GND
OUT−GND
OUT−VS
P
R
V0
V0
V0
φ
φ
F
F
φ
φ
t0
t0
φ
φ
φ
φ
P1 := R φ φ φ T
Q1 := φ φ φ φ T
P2 := V0 φ φ φ T
Q2 := φ φ φ φ T
P3 := V0 F t0 φ T
Q3 := φ φ φ φ T
P4 := V0 F t0 φ T
Q4 := V0 F t0 φ T
Q
φ
φ
φ
V0
φ
φ
φ
F
φ
φ
φ
t0
φ
φ
φ
φ
min
Connection
Stimulation
Acquisition
φ
φ
S
Note
Group
(Purpose in Table 2)
Next, we need to choose a DUT and list its pin variations.
We assume that the DUT has K 4 pins and only K 4 of
its pin variations are to be concerned (Fig.5).
S:
M:
φ:
PV m k act max
S
S
φ
φ
φ
S
QV 2 m k min act max
φ
φ
S
φ
φ
M
φ
φ
S
test specification to be assigned.
measurement result provided by instruments.
”don’t care”.
PV
m 2 φ φ
φ
φ φ
φ
Actual : 2V 10kHz 0s
φ
φ φ
φ φ
φ
φ φ
φ
Min : φ φ
φ
φ
φ
φ
φ φ
φ
φ φ
φ
Max : φ φ
φ
φ φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
PV
m 3 1kΩ φ
φ
φ
φ
φ
φ
φ
φ φ
φ
φ
φ
φ
φ
φ
φ φ
φ
φ
φ
φ
φ
φ
φ φ
φ
φ
1V
10kHz
0s
φ
φ φ
φ
φ
φ
φ
φ
φ
φ φ
φ
φ
3V 10kHz 0 1ms φ
Paper 38.1
1085
QV
1 m 2 0 0 0
0 0 0
0 0 0
0 0 0
QV
2 m 2 φ φ φ
φ φ φ
Actual : φ φ φ
φ φ φ
φ φ φ
φ φ φ
Min : φ φ φ
φ φ φ
φ φ φ
φ φ φ
Max : φ φ φ
φ φ φ
0 0
0 0
QV
1 m 3 0 0 0
0 0 0
0 0 0
1 0 0
QV
2 m 3 φ φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
Table 6 shows five groups of basic functions. v t , v1 t ,
v2 t , i t , i1 t and i2 t are the same as those used in Table
2, namely the basic signals listed in Table 1.
0 0
0 0
Table 6: Groups of basic functions
φ φ φ φ
φ φ φ
φ
φ φ φ qv2 m 3 4 1 φ φ φ φ
φ φ φ φ
φ φ φ
φ
φ φ φ 1 9V
φ φ φ φ
φ φ φ φ
φ φ φ
φ
φ φ φ 2 1V
φ φ φ
Assuming that in one test step maximal U 4 test parameter
will be tested, Y T S m and ΛT S m can be represented by
Y T S m
ΛT S m y m 1
λ m 1
m 1 φ φ φ T
T
λ m 1 φ φ φ
y
:
A10k
y m 1
qv2 m 3 4 1 pv m 2 3 1 where qv2 m 3 4 1 is the measurement value in the fourth
row and first column of QV 2 m 3 act , and pv m 2 3 1 the
value in the third row and first column of PV m 2 act .
5 ATE Architecture
5.1 Definition of a Set of Basic Functions
A basic function is defined as a combination of the following
items: (1) the type of a basic port; (2) a basic signal; (3) the
purpose (stimulation or acquisition).
A basic port means a possible port that the ATE hardware
modules may have. There are four types of such ports that
are usually used (Fig.6):
(a)
(b)
(c)
(d)
Two pins for one signal
Three pins for two signals (one pin is common)
Four pins for two separate signals
Four pins for one signal (Kelvin connection)
H
v t i t H1
L1
H1
H2
v1 t v2 t i1 t i2 t v1 t v2 t i1 t i2 t H2
L2
L
L
(a) Pin−Pin (b) Pin−Pin−Pin (c) Pin-Pin ( 2)
Fig. 6: Types of a basic port
Paper 38.1
1086
Group
Basic Signal(s)
Type of a
Basic Port
Purpose
G 2V
G 2I
G 3V
G 3I
G 4V
G 4I
G 5V
G 5I
G 6V
v t i t
v t i t
v1 t i1 t v1 t i1 t v t Pin-Pin
Pin-Pin
Pin-Pin
Pin-Pin
Pin-Pin-Pin
Pin-Pin-Pin
Pin-Pin ( 2)
Pin-Pin ( 2)
Pin-Pin (FS)
Stimulation
Stimulation
Acquisition
Acquisition
Acquisition
Acquisition
Acquisition
Acquisition
Stimulation
v2 t i2 t v2 t i2 t Notice that the basic functions for fINSTs and for cINSTs
are different. In Table 6, G 2V , G 2I and G 6V are noted by
”stimulation” and the others (G 3V , G 3I, G 4V , G 4I, G 5V
and G 5I) by ”acquisition”. For the fINSTs, ”stimulation”
means the generation of a basic signal, while ”acquisition”
means the acquisition of a basic signal. For the cINSTs,
”stimulation” means the transmission of a basic signal to be
stimulated, while the ”acquisition” means the transmission
of a basic signal to be acquired.
5.2 Definition of Properties for a Basic Function
A number of properties are used for describing a basic function in detail. The properties are divided into 5 groups (Table 7). Fig.7 shows the assignment of these groups for different basic modules.
Function
(Generation)
Range
Port
(Output) (Output)
(a) fINST module (used
as
source)
Port
Range
Function (Input) (Input) (Measurement)
(b) fINST module (used as meter)
Port
(Input)
Range
(Input)
Function
Range
Port
(Processing) (Output) (Output)
(c) cINST module (used for transmission of a signal)
Fig. 7: A basic module
HF
HS
v t
LF
LS
(d) Pin−Pin (FS)
The properties E1-E7 describe the input and/or output
port of a basic module: Name is the port name; Type indicates the type of the port (Fig.6); Pin contains the names
of the port pins and Connector the names of their corresponding electrical nodes in the ATE; Relay provides the
information about if the port is controllable; switchCmd and
switchPar contain the commands to switch the port on and
off and their parameters (e.g. swiching time).
Table 7: Properties of a basic module
Group
Port
(E1-E7)
Range
(E8-E12)
Function
(Generation)
(E13-E17)
Property
1
1
4
4
4
2
2
1
1
1
1
1
1
1
rangePName
rangePPar
rangeP2Par
rangePSetCmd
rangePSetPar
1
2
2
2
2
1
1
1
1
1
PPar
PVSetCmd
PVSetPar
PStartCmd
PStartPar
ΓP
2
2
2
8
QV1
rangeQName
rangeQPar
QV1SetCmd
Function
(Measurement) QV1SetPar
(E18-E29)
QModeName
QModeType
QModePar
QModeSetCmd
QModeSetPar
QStartCmd
QStartPar
Function
(Processing)
(E30-E34)
Size of Matrix
Name
Type
Pin
Connector
Relay
switchCmd
switchPar
SModeName
SModeType
SModePar
SModeSetCmd
SModeSetPar
1
1
1
1
1
1
1
1 RP
Γ P RP
ΓP2 RP
1 RP
1 RP
ΨP
1
1
1
1
1
1
1
1
1
1 1
1 1
2 1
2 1
2 1
1 1
1 1
Π Q ΨQ 2 1
2 1
1 1
4 1
ΓQ
ΓQ
ΓQ
ΓQ
ΓQ
ΓQ
ΓQ
ΓQ
ΓQ
ΓQ
ΓQ
ΓQ
1
1
ΠS
2
2
MS
MS
MS
MS
MS
1
1
ΨS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RQ
RQ
RQ
RQ
MQ
MQ
MQ
MQ
MQ
MQ
MQ
1
1
1
1
1
The properties E8-E12 describe the input and/or output ranges of a basic module. rangePName contains the
names of the ranges. Each range uses two parameter blocks:
rangePPar stands for parameters of the signal to be generated or measured and rangeP2Par for the other parameters, for example input impedance. rangePSetCmd and
rangePSetPar contain the commands for setting the ranges
and their parameters (e.g. setting time).
The properties E13-E17 describe the function of a basic
module used as source. PPar describes the possible values
of the parameters of the signal to be generated. PVSetCmd
and PVSetPar contain the commands and their parameters to
set PPar. PStartCmd and PStartPar contain the commands
and their parameters to start/stop a signal run.
The properties E18-E29 describe the function of a basic module used as meter. QV1 contains the measurement
parameters. Each measurement parameter may have some
measurement ranges. rangeQName contain the names of
the measurement ranges for all measurement parameters.
rangeQPar contains their limiting values. QV1SetCmd and
QV1SetPar contain the commands and their parameters to
choose a measurement parameter and its range. Each measurement parameter may have some measurement modes
(QMode). SINGLE and MULTIPLE are for example names
of two modes contained in QModeName. These two modes
can be represented by one standard waveform whose index
and parameters are contained in QModeType and QModePar, respectively. QModeSetCmd and QModeSetPar contain the commands and their parameters to set the modes.
QStartCmd and QStartPar contain the commands and their
parameters to start/stop the measurement.
The properties E30-E34 describe the function of a basic
module used for the transmission of a signal. During the
transmission, the signal may be ”processed” in some ways
called processing modes (SMode). SModeName, SModeType and SModePar describe the names, types (e.g., amplifier, comparator) and parameters (e.g., gain for amplifier,
reference voltage for comparactor) of the modes, respectively. SModeSetCmd and SModeSetPar contain the commands and their parameters to set the modes.
5.3 Representation of an Instrument and its Properties
Let Fi i 1 I, be a basic function. Let Mni j j 1 J, be a basic module of Fi for an instrument instn
and Eni j E1 E2 E34 Table 7 denote a property of
Mni j . Suppose that I is the number of basic functions of a
description system and J is the number of basic modules for
each basic function in the description system. The instrument instn can be described by two matrices MVn (module
value) and EVn (property value):
MVn
EVn
evni j where
mvni j
evni j
I J
mvni j (16)
I J
(17)
1 if Mni j exists;
0 if Mni j does not exist.
Value of Eni j if mvni j
Φ (”don’t care”) if mvni j
(18)
1
0
(19)
5.4 Signal Path
Fig.3 shows the signal paths of a basic module (fINST).
Suppose that each basic module (fINST) Mni j has A signal
paths signalPathni j a a 1 2 A, and each signal path
signalPathni j a has B basic modules Tni j ab b 1 2 B.
Let Wni j ab denote a property of Tni j ab . All signal paths of
Mni j can then be described by two matrices TVni j (module
value) and WVni j (property value):
TVni j
WVni j
tvni j ab A B
wvni j ab A B
(20)
(21)
where
Paper 38.1
1087
tvni j ab
ñ j˜ if one Mñi j˜ exists;
φ φ
if no Mñi j˜ exists.
Value of Eñi j˜ if tvni j ab
φ (”don’t care”) if tvni j ab
wvni j ab
ñ j˜ ;
φ φ The matrices MVn , EVn and PaMVn h are used to represent an instrument, including fINST and cINST. The matrices TVni j , WVni j and PaTVni j g are used to represent
the signal paths of a basic module (fINST). Together, all
these matrices describe an ATE architecture. These matrices could, for example, be provided by ATE vendors as
online documents together with their ATEs.
Note that ñ is the index of a cINST and j˜ the index of a basic
module of the cINST. Eñi j˜ E1 E2 E34 Table 7 .
5.5 Concurrency of Instruments
To describe the concurrency of basic modules, a so-called
functional pattern is introduced.
For an instrument, a functional pattern is defined by
PaMVn h
pamvni j h I
J
h 1 Hn
(22)
where Hn is the number of the functional patterns.
For the signal paths of a basic Module Mni j (fINST), a
functional pattern is defined by
(23)
PaTVni j g patvni j ab g A B g 1 Gni j
where Gni j equals the number of the functional patterns.
For pamvni j h and patvni j ab g, the following holds:
1 Mni j (Tni j ab ) can be used in parallel;
0 Mni j (Tni j ab ) can not be used in parallel;
pamvni j h
R Mni j (Tni j ab ) can be used in parallel,
patvni j ab g and this is switchable;
φ Mni j (Tni j ab ) does not exist.
5.6 An Example
We begin by defining a set of basic functions. To keep the
dimension of matrices small, we choose I 4 and assume
that each basic function has maximal J 4 basic modules.
F1 : DC voltage source F3 : DC voltage meter
F2 : DC current source F4 : DC current meter
Now consider a PMU that can perform all these basic
functions (F1 , F2 , F3 and F4 ) and has only one basic module for each basic function (Mn11 , Mn21 , Mn31 and Mn41 ).
As an example, two matrices are given in the following:
1 0 0 0
1 0 0 0
1 0 0 0
0 0 0 0
MVn PaMVn h 0 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
The left matrix shows all its basic modules. The right matrix
shows one of its functional patterns. It says that the PMU
can provide the basic functions F1 and F4 simultaneously.
The properties EVn have the same form like MVn above.
The difference is that their elements are not 0s or 1s, but
block matrices listed in Table 7.
6 Actual Results
6.1 Theoretical Part
The matrices SV T S m , PV T S m , QV 1T S m , QV 2T S m ,
Y T S m and ΛT S m are used to represent the test specification of a DUT. The input of the test specification means
assigning values to these matrices.
Paper 38.1
1088
fINST−Module
fINST−Module
fINST−Module
4
4
4
(1)
Signal Path
Signal Path
Signal Path
4
DIB Channel
4
DIB Channel
4
DIB Channel
(2)
SIV m k sivib I FIV m k f ivi I
(3)
B
FMV m k f mvi I SMV m k smvib I FEV m k f evi I
SEV m k sevib I Pin
Variation
4
k
B
B
DMV m k dmvi I
DEV m k devi I
Fig. 8: Test configuration
The test concept is a set of so-called test configurations.
A test configuration (Fig.8) is a realization for SV m k ,
PV m k and QV 1 m k and consists of three parts: (1)
FIV m k , FMV m k and FEV m k denote the used fINSTs, their basic modules and the properties of these modules, respectively; (2) SIV m k , SMV m k and SEV m k describe the corresponding signal paths up to the ATE
interface-to-DUT and denote the used cINSTs, their basic
modules and the properties of these modules, respectively;
(3) DMV m k and DEV m k describe the corresponding
signal paths on the DIB and denote the needed basic functions and their properties, respectively.
Based on the above descriptions, generating a test concept means creating the test configurations for all pin variations and all test steps. More precisely, it is the following
(Fig.8): (1) select a basic module (fINST) for each basic
state; (2) select a corresponding signal path; (3) select a corresponding basic channel (DIB). The basic states and basic
functions have been defined in such a way that every basic
function is used to realize one basic state. Thus, determining
if a basic module is suitable for a basic state means comparing the corresponding properties of both. So, in general, it
is not difficult to obtain a set of suitable basic modules and
a set of suitable signal paths for each basic state.
Generating an optimal test concept means distributing
the suitable basic modules and the corresponding signal
paths according to some optimal criteria. Our approach
makes a contribution to this in such a way that the information about the test specification and the ATE architecture can be ”operated” mathematically and the results
can be used for the optimization, independent of the used
criteria. For example, the binary addition M
m 1 SV m k produces a matrix that indicates which basic states are
desired for one pin variation during all test steps; The
decimal addition ∑M
m 1 SV m k produces a matrix that
gives the frequencies with which the basic states are de-
sired for one pin variation during all test steps; The
operations Min Max PV m k m 1 M produce
two matrices that give the boundary values of the property of the basic states for one pin variation during all
test steps. Similarly, Kk 1 SV m k , ∑Kk 1 SV m k and
Min Max PV m k k 1 K produce the matrices
that give the desired basic states, their frequencies and the
boundary values of their property for all pin variations in
one test step, respectively. Similar operations can be used
for the matrices representing the ATE architecture.
6.2 Practical Part
We have defined 239 basic states for describing test specifications (their properties are defined at a higher level). Considering AD1674 (12bit ADC, 28 pins) as example, five
representative tests (power supply current, input resistance,
logic input voltage, input output delay and a functional test)
are selected from the device data sheet and represented by
matrices (using a subset of defined basic states).
We have defined 231 basic functions for describing ATE
architectures. Considering M3650 as example, the following instruments are analyzed: VM (voltmeter), VIS10 (voltage/current source), HRSG (high resolution signal generator), HRSD (high resolution signal digitizer), PMU, TMU,
BUS, DC MX (matrix), as well as the driver and comparator
of DPINs (pin electronics).
In order to describe a complete test specification and a
complete ATE architecture, a reasonable description system
with, for example, I 512, J 1024, ΓQ 8 and MQ 8
is to be used. This means that the instruments are allowed
to have 512 different basic functions and 1024 basic modules for each basic function. A basic module used as meter
is allowed to measure 8 parameters and have 8 measurement modes for each parameter. In this case the property
QModeName (Table 7) is a 512 1024 8 8 matrix.
So we have started to develop a tool with the following
functions: input a test specification, manipulate the corresponding matrices and output their boundary data. Here,
an adequate method for storing the needed matrices using
sparse matrix techniques is to be applied (see Section 7.4).
As the second step, this tool can be extended with the following functions: input an ATE architecture, manipulate the
corresponding matrices and output their boundary data. So
far, the tool can be used as an online planner for test engineers to manually create their test concepts. On this basis,
integrating algorithms for the generation of a test concept
will be relatively easy.
7 Discussion
7.1 Effect on DIB Development
DMV m k and DEV m k shown in Fig.8 can be used as a
clear specification for DIB development, including circuit
design and DIB testing. The matrices M
m 1 DMV m k ,
∑M
m 1 DMV m k and Min Max PV m k m 1 M can provide the information about the desired basic functions, their frequencies and the boundary values of their
properties for the DIB with respect to the pin variation k,
respectively. For example, the following information can
be given: a DC current signal, a DC voltage signal and a
sine voltage signal should be applied once, twenty times
and twice to a pin, respectively; for the DC voltage signal
two sources will be used (PMU5 and VIS10 1); VIS10 1
is used for the test steps 5 and 6 (two times), the voltage
value ranges from 2.0 V to 4.0V; PMU5 is used for the other
test steps (18 times), the voltage value ranges from 0.0V to
2.0V. How much information can be provided depends on
the properties prepared for the DIB specification.
7.2 Effect on Test Program Development
The test program specification has two forms: (1) matrices
shown in Fig.8; (2) a sequence of standard commands describing the actions of the needed resources, including fINSTs, cINSTs and DIB channels. The commands for a meter
can for example look as follows:
SELECT
< INST n, MODULE i j >
CONNECT < IN >
SET
< IN, range >
SET
< QV, QV >
SET
< QMODE, mode2, mode2Par >
START
< Q, startPar >
This means the following: select the Instrument instn and
its module Mni j ; connect its input port; set its input range
to range; set the instrument to measure the parameter specified by QV (e.g. DC voltage); set the measurement mode to
mode2 (e.g. MULTIPLE) and its parameters to mode2Par
(e.g., four measurements should be done, the first measurement occurs with 20 µs delay and each further measurement
occurs after 30 µs); start the measurement using the parameters contained in startPar.
The properties with the suffix Cmd listed in Table 7 are
designed to be used in mapping the test program specification (presented in the second form) into the test program
(test code). With such a test program, the utilization of the
hardware resources is optimized. However, the optimization
at the code level is still needed.
7.3 Issues about Limitations
The basic states and basic functions defined in this paper
may need to be extended for completeness, since completeness can only be realized in the context of one specific application area.
There is a question of abstraction levels. For example, the
issues like accuracy, repeatability, jitter and noise can only
then be considered, if the corresponding data are contained
in the properties.
The properties of the basic states and the basic functions
have been defined in such a way that they are comparable
Paper 38.1
1089
with each other. But even so there are some parameters that
a basic module possesses and a basic state does not possess,
for example, slew rate. This leads to the fact that either this
parameter is given as a variable in the generated concept
or additional information is requested during the generation
process.
In principle, there is no constraint on how an ATE should
be decomposed into individual instruments. An instrument
can be a voltmeter, a matrix, a transmission line, a switcher,
a connector or the whole pin electronics. In general, the
finer the decomposition, the better for the flexibility and the
reusability. But the more data are needed to represent the
whole ATE.
7.4 Data Amount
According to our approach a large number of data are to
be stored. If we store the matrices directly, the problem of
storage space may arise. For example, with I 512, the
matrices for the test specification per test step and per pin
variation may contain 64 5K data (binary numbers, strings
or values) and with I 512 and J 1024, a fINST may
contain 2838 5M data. However, this problem can be solved
by using sparse matrix techniques, since it was observed that
all these matrices are very sparsely occupied.
For example, for one pin variation in one test step often
only one basic state is used. Replacing I 512 by a mean
value for example I¯
2, the data to be stored will be reduced
from 64 5K to 0 25K. As for the ATE instruments, a PMU,
for example, usually has only four basic functions and one
basic module for each basic function. Using a mean value,
for example I¯
16 and J¯
16 for I 512 and J 1024, the
data to be stored for a fINST can be reduced from 2838 5M
to 1 39M. There are other possibilities to reduce the amount
of data. Here we will not go into detail. To conclude, it is
possible to keep the amount of data to be stored within a
reasonable scope by using sparse matrix techniques.
8 Conclusion
This paper proposed a new approach to describe test specifications and ATE architectures at the electrical level. The
approach is application oriented, since the description is tailored to explicitly provide the information which a test engineer requires for his DIB and test program development.
The test specification and ATE architecture are represented by mathematical matrices. So our approach offers
possibilities to use mathematical algorithms to derive a test
concept for the DIB and test program development.
To implement this approach in a tool, a large number of
data are to be stored. However, it was observed that all these
matrices are very sparsely occupied. So, sparse matrix techniques can be used.
Acknowledgements
This work was supported in part by the German BMBF
Paper 38.1
1090
within the scope of MONARCH (Project Ref: 01M3057C)
References
[1] S. C. Bateman and W. Kao. Simulation of an Integrated Design and Test Environment for Mixed-Signal
Integrated Circuits. In Proc. International Test Conference, pages 405–414, 1992.
[2] E. Sax, G. Krampl, M. Miegler, and S. Sattler. A Common Mixed-Signal Testbench for Design Verfication
and Test. In Proc. IEEE International Mixed Signal
Testing Workshop, pages 35–40, 1999.
[3] H. Grams, E. Eckert, W. Hartl, I. Thorbergsson, and
W. Tenten. Status of Virtual Test and Visions. In
Proc. IEEE International Mixed Signal Testing Workshop, pages 182–186, 2000.
[4] G. Krampl, M. Rona, and H. Tauber. Test Setup Simulation - a High-Performance VHDL-based Virtual Test
Solution Meeting Industrial Requirements. In Proc.
International Test Conference, pages 870–878, 2002.
[5] T. P. Warwhick. What a Device Interface Board Really
Costs: An Evoluation of Technical Consideration for
Testing Products Operating in the Gigabit Region. In
Proc. International Test Conference, pages 555–564,
2002.
[6] K. Helmreich. Test path Simulation and Characterization. In Proc. International Test Conference, pages
415–423, 2001.
[7] D. E. McFeely. The Process and Challenges of a HighSpeed DUT Board Project. In Proc. International Test
Conference, pages 565–573, 2002.
[8] SIA. International technology roadmap for semiconductors: Test and test equipment, 2003.
[9] M. Burns and G. W. Roberts. An Introduction to
Mixed-Signal IC Test and Measurement. Oxford University Press, 2001.
[10] D. Johansen. Definition and Description of an Automated Mixed Signal Test Program Generator. In Proc.
IEEE International Mixed Signal Testing Workshop,
pages 105–109, 1999.
[11] IEEE 1450 - Standard Test Interface Language
(STIL), 2003. URL http://grouper.ieee.
org/groups/1450/.
[12] M. Miegler. Konzeption einer Datenbasis zur Spezifikation und Generierung von Prüfprogrammen für
gemischt analog-digitale integrierte Schaltungen. VDI
Verlag GmbH, 1999.
[13] IEEE SCC20 Test Description SubCommittee, 2003.
URL http://grouper.ieee.org/groups/
scc20/td/.
[14] L. A. Shombert and J. W. Sheppard. A Behavior Model
for Next Generation Test Systems. Journal of Electronic Testing: Theory and Applications, 13(3), December 1998.