Sequential Circuits
Principles of VLSI Design
CMPE 413
Sequential Circuits
Combinational Circuits
Outputs depend on the current inputs
Sequential Circuits
„ Outputs depend on current and previous inputs
„ Requires separating previous, current and future
„ Called states or tokens
„ Example: Finite State Machines (FSMs), Pipelines
clk
in
clk
clk
clk
out
CL
Finite State Machine
CL
CL
Pipeline
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Principles of VLSI Design
Sequential Circuits
CMPE 413
Sequential Circuits
If tokens moved through pipeline at constant speed, no sequencing elements will be needed
Ex: Fibre-optic cable, called wave pipelining in circuits
However, dispersion is high in most circuits
We need to delay fast tokens, so that they don't catch up with slow tokens
Use flip-flops to delay fast tokens so that they move through exactly one stage per cycle
Inevitably adds some delay to slow tokens
Makes circuit slower than just the logic delay
Called sequencing overhead
Sometimes called clocking overhead
But it applies to asynchronous circuits too
Inevitable side effect of maintaining sequence
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Sequential Elements
Latch
Level sensitive
Transparent latch
D latch
Flip-Flop
Edge triggered
Master-slave flip-flop
D flip-flop, D register
clk
Q
D
Flop
D
Latch
clk
Q
clk
D
Q (latch)
Q (flop)
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Sequential Elements: Latch
Pass Transistor Latch
φ
D
Q
Pros:
„ Tiny
„ Low clock loads
Cons:
‰ Vt drop
‰ nonrestoring
‰ backdriving
‰ output noise sensitivity
‰ dynamic
‰ diffusion input
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Principles of VLSI Design
Sequential Circuits
CMPE 413
Sequential Elements: Latch
Transmission Gate Latch
„ No Vt drop
‰ Requires inverted clock
Inverting Buffer
Pros:
„ Restoring
„ No backdriving
„ Fixes either:
output noise sensitivity
Or diffusion input
Cons:
‰ Inverted output
φ
D
Q
φ
φ
X
D
φ
Q
φ
D
Q
φ
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Principles of VLSI Design
Sequential Circuits
CMPE 413
Sequential Elements: Latch
Tristate feedback
„ Static
‰ Backdriving risk
φ
X
D
Q
φ
φ
Static latches are now essential
φ
Buffered Input
φ
„ Fixes diffusion input
„Noninverting
X
D
φ
Q
φ
φ
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Principles of VLSI Design
Sequential Circuits
CMPE 413
Sequential Elements: Latch
Buffered Output
„ Non backdriving
Widely used in standard cells
„ Very robust (important feature)
‰ Rather large
‰ Rather slow (1.5 - 2 FO4 delays)
‰ High clock loading
φ
X
D
φ
φ
φ
Datapath Latch
„ Smaller, faster
‰ Unbuffered input
Q
φ
Q
X
D
φ
φ
φ
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Sequential Elements: Flip-Flop
Flip-Flop
Built as a pair of back-to-back latches
φ
φ
X
D
Q
φ
φ
φ
φ
Q
X
D
φ
Q
φ
φ
φ
φ
φ
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Sequential Elements
Enable
Ignore clock when enable is inactive
Mux: increase latch D-Q delay
Clock-gating: increase enable setup time, skew
Symbol
Multiplexer Design
Clock Gating Design
φ en
0
en
D
Q
D
1
0
Q
Flop
φ
Flop
Q
en
φ en
φ
D
Latch
1
D
Q
Q
D
en
Flop
Latch
D
Latch
φ
φ
Q
en
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Sequential Elements
Reset
Force output low when reset is asserted
Synchronous vs. asynchronous
φ
Q
D
reset
Synchronous Reset
φ
Q
φ
reset
D
φ
Q
reset
φ
reset
D
Flop
Symbol
D
Latch
φ
Q
Q
φ
φ
φ
φ
φ
φ
φ
Asynchronous Reset
Q
φ
φ
Q
φ
φ
reset
reset
D
D
φ
φ
φ
φ
φ
φ
reset
reset
φ
φ
φ
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Sequential Elements
Set / Reset
Set forces output high when asserted
Flip-Flop with asynchronous set and reset
φ
φ
reset
set
D
φ
φ
φ
Q
φ
set
reset
φ
φ
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Timing Diagrams
A
Combinational
Logic
A
tpd
Y
tcd
Y
tpd
Logic Prop. Delay
tcd
Logic Cont. Delay
tpcq
Latch/Flop Clk-Q Prop Delay
tccq
Latch/Flop Clk-Q Cont. Delay
tpdq
Latch D-Q Prop Delay
tpcq
Latch D-Q Cont. Delay
tsetup
Latch/Flop Setup Time
thold
Latch/Flop Hold Time
Flop
D
Q
tsetup
thold
D
tpcq
Q
clk
clk
D
Latch
Contamination
and
propogation delays
clk
clk
tccq
tsetup
thold
tccq tpcq
Q
D
tcdq
tpdq
Q
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Sequencing Methods
Tc
 Flip-Flops
clk
Combinational Logic
φ1
tnonoverlap
tnonoverlap
Tc/2
φ2
Combinational
Logic
Combinational
Logic
Half-Cycle 1
tpw
φp
Combinational Logic
Latch
φp
Latch
φp
φ1
Latch
Latch
φ1
Latch
φ2
Half-Cycle 1
Pulsed Latches
 Pulsed latches
2-Phase Transparent Latches
 2-Phase latches
Flop
clk
Flop
Flip-Flops
clk
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Max-Delay: Flip-Flops
T C = t pcq + t pd + t setup
t pd ≤ T C − ( t setup + t pcq )
sequencing delay
clk
Q1
Combinational Logic
D2
F2
F1
clk
Tc
clk
Q1
tsetup
tpcq
tpd
D2
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Max-Delay: 2-Phase Latches
t pd = t pd1 + t pd2 ≤ T c − ( 2t pdq )
Q1
Combinational
Logic 1
D2
φ1
Q2
Combinational
Logic 2
D3
L3
φ2
L2
D1
L1
T c ≥ t pdq1 + t pd1 + t pdq2 + t pd2
φ1
Q3
φ1
φ2
sequencing delay
Tc
D1
Q1
D2
Q2
tpdq1
tpd1
tpdq2
tpd2
D3
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Max-Delay: Pulsed Latches
T C ≥ max ( t pdq + t pd ,t pcq + t pd + t setup − t pw )
t pd ≤ T C − max ( t pdq, t pcq + t setup − t pw )
φp
Q1
D2
Combinational Logic
L2
D1
L1
φp
sequencing delay
Q2
Tc
D1
(a) tpw > tsetup
tpdq
Q1
tpd
D2
φp
tpcq
Q1
Tc
tpd
tpw
tsetup
(b) tpw < tsetup
D2
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Min-Delay: Flip-Flops
t cd ≥ t hold − t ccq
F1
clk
Q1
CL
clk
F2
D2
clk
Q1 tccq
D2
tcd
thold
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Min-Delay: 2 Phase Latches
t cd1, t cd2 ≥ t hold − t ccq − t nonoverlap
Hold time reduced by nonoverlap
L1
φ1
Q1
CL
D2
φ1
L2
φ2
Paradox: Hold applies twice each cycle
vs. only once for flops
But flops have two latches !!!
tnonoverlap
tccq
φ2
Q1
D2
tcd
thold
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Principles of VLSI Design
Sequential Circuits
CMPE 413
Min-Delay: Pulsed Latches
t cd ≥ t hold − t ccq + t pw
Hold time increased by pulse width
L1
φp
Q1
CL
D2
φp
L2
φp
tpw
thold
Q1 tccq
tcd
D2
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Principles of VLSI Design
Sequential Circuits
CMPE 413
Time Borrowing
In a flip-flop based system
„ Data launches on one rising/falling edge
„ Must setup before next rising/falling edge
„ If it arrives late, system fails
„ If it arrives early, time is wasted
„ Flops have hard edges
In a latch-based system
„ Data can pass through latch when transperent
„ Long cycle of logic can borrow time into the next cycle
„ As long as each loop completes in one cycle
This mechanism is called time borrowing
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Time Borrowing
φ1
φ2
Combinational Logic
Borrowing time across
half-cycle boundary
Combinational
Logic
Borrowing time across
pipeline stage boundary
φ2
Combinational Logic
Latch
(b)
Latch
φ1
φ1
Latch
φ2
Latch
(a)
Latch
φ1
Combinational
Logic
Loops may borrow time internally but must complete within the cycle
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Time Borrowing
How much borrowing?
2 phased latches:
TC
t borrow ≤ ------- − ( t setup + t nonoverlap )
2
pulsed latches:
t borrow ≤ t pw − t setup
φ2
Q1
Combinational Logic 1
D2
L2
D1
L1
φ1
Q2
φ1
φ2
tnonoverlap
Tc
Tc/2
Nominal Half-Cycle 1 Delay
tborrow
tsetup
D2
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Principles of VLSI Design
Sequential Circuits
CMPE 413
Clock Skew
clk
F1
Q1
We have assumed zero clock skew
D2
Tc
Clock really have uncertainty in arrival time
decrease max-delay
increases min-delay
decreases time borrowing
Combinational Logic
F2
clk
clk
tpcq
Q1
tskew
tpdq
tsetup
D2
clk
Q1
CL
clk
D2
t cd ≥ t hold − t ccq + t skew
F2
t pd ≤ T C − ( t pcq − t setup − t skew )
F1
Clock Skew: Flip-flops
tskew
clk
thold
Q1 tccq
D2
tcd
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Sequential Circuits
Principles of VLSI Design
CMPE 413
Clock Skew: Latches
2 phased latches
t pd ≤ T c − ( 2t pdq )
Q1
Com binational
Logic 1
D2
φ1
Q2
Com binational
Logic 2
D3
L3
φ2
L2
D1
L1
φ1
Q3
φ1
φ2
t cd1, t cd2 ≥ t hold − t ccq − t nonoverlap + t skew
TC
t borrow ≤ ------- − ( t setup + t nonoverlap + t skew )
2
pulsed latches
t pd ≤ T C − max ( t pdq, t pcq + t setup − t pw + t skew )
t cd ≥ t hold − t ccq + t pw + t skew
t borrow ≤ t pw − ( t setup + t skew )
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