Valter Bonvicini, Giulio Orzan, Nicola Zampa, Gianluigi
Zampa
INFN Trieste
CALOCUBE meeting
Firenze, 20 febbraio 2015
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R&D carried on in Trieste through the CSN 5
experiments CASIS and CASIS2
Several prototypes designed, realized and tested
CASIS1.2A ASIC (used for the CaloCube prototypes
realized so far):
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Double-gain (double-range) CSA
Double-correlated sampling, MUX and output buffer
Input calibration circuit (with arbitrary channel pattern)
16 channels
Noise: 2700 e- + 8e-/pF
Power consumption: 2.8 mW/channel
Dynamic range (low gain): 53 pC
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2.9 mm
5.22 mm
• 16 front-end channels, multiplexed and buffered onto a single analog output bus
• Input calibration circuit (arbitrary pattern of channels selectable)
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Foreword: this is “a mid-term” redesign (not the final
version).
28 channels, no ADC
Deadline: MPW run Europractice with AMS CMOS
0.35 C4B3 on April 7th, 2015 (no time to loose…!!)
Given the previous yields, we expect > 50 good chips
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Resizing of the input transistor to match the CaloCube
total input capacitance (ClargePD + Cstray), with the same
bias current (better gm  better series noise)
Daisy-chain possibility of the calibration registers
(important in view of the experimental applications)
Change the reference of the output buffer (no Vped but
an intermidiate voltage)
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• 16 FE channels with A/D conversion
function integrated in the ASIC;
• 1 12-bit cyclic ADC /channel with
capacitor averaging and digital
correction;
5300 µm
• Design submitted in August 2013
(prototypes arrived at the end of 2013);
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µm
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250 µm
2970 µm
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Details of one chip (AMS 0.35 um CMOS C35B4 technology)
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Detail of the test boards designed and realized in Trieste for the characterization
of the new ASIC
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CASIS1.2B chip in
CQFP120 package
“Daughter board”
“Mother board”
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Test set-up in Trieste
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