Difference between
Microprocessor and Microcontroller
The term Microprocessor And Microcontroller have always been
confused with each other. Both of them have been designed for real time
application. They share many common features and at the same time they have
significant differences. Both the IC’s i.e., the microprocessor and microcontroller
cannot be distinguished by looking at them. They are available in different
version starting from 6 pin to as high as 80 to 100 pins or even higher depending
on the features.
Difference between
Microprocessor and Microcontroller
 Microprocessor is an IC which has only the CPU inside them i.e. only the
processing powers such as Intel’s Pentium 1,2,3,4, core 2 duo, i3, i5 etc. These
microprocessors don’t have RAM, ROM, and other peripheral on the chip. A
system designer has to add them externally to make them functional. Application
of microprocessor includes Desktop PC’s, Laptops, notepads etc.
 But this is not the case with Microcontrollers. Microcontroller has a CPU, in
addition with a fixed amount of RAM, ROM and other peripherals all embedded
on a single chip. At times it is also termed as a mini computer or a computer on a
single chip. Today different manufacturers produce microcontrollers with a wide
range of features available in different versions. Some manufacturers are ATMEL,
Microchip, TI, Freescale, Philips, Motorola etc.
8086 Microprocessor
Contents:
1) Register Organization of 8086
2) General Purpose Registers
3) Segment Registers
4) Pointers and Index Registers
5) Flag Register
6) Architecture of 8086
6.1. Bus Interface Unit
6.2. Execution Unit
Register Organization of 8086
 The 8086 has a powerful set of registers. It includes general purpose registers,
segment registers, pointers & index registers and flag registers. The register
organization of 8086 is also called as programmer’s model of 8086.
 The registers shown in the programmer’s model is accessible only to
programmer .
AH
AL
BH
BL
CH
CL
DH
DL
a) General Purpose
Registers
SP
b) Segment Registers
BP
SI
DI
IP
c) Flag Registers
d) Pointer and Index Registers
General Purpose Registers
 The 8086 has four 16 – bit general purpose registers labeled AX, BX, CX and
DX. Each 16 – bit general purpose register can be split into two 8 – bit registers.
The Letters L and H specify the lower and higher bytes of a particular register.
 The General Purpose Registers are either used for holding data, variables, and
intermediate results temporarily. They can also be used as a counters or used for
storing offset address for some particular addressing modes. The register AX is
used as 16 – bit accumulator where as register AL is used as 8 – bit accumulator.
The register BX is also used as offset storage for generating physical addresses in
case of certain addressing modes. On the other hand, the register CX is also used
as a default counter in case of string and loop instructions.
Segment Registers
These are used to hold the upper 16 – bits of the starting addresses of the four
memory segments, on which 8086 works at a particular time.
Functions of Segment Registers
 The CS Register holds the upper 16 – bits of the starting address of the segment
from which the BIU is currently fetching the instruction code byte.
 The SS Register is used for the upper 16 – bit of the starting address for the
program stack.
 ES Register and DS register are used to hold the upper 16 – bits of the starting
address of the two memory segments which are used for data.
Pointers and Index Registers
 All segment registers are 16 – bit wide. But it is necessary to generate 20 – bit
address on the address bus. To get 20 – bit physical address one or more pointer or
index registers are associated with each segment Register.
The pointer registers IP, BP and SP are associated with Code, Data and Stack
Segments, respectively. They hold the offset within the code, data and stack
segments, respectively.
The index registers DI and SI are used as a general purpose registers as well as
for offset storage in case of indexed, based indexed and relative indexed
addressing modes. The detailed description of pointers and index register.
Flag Register
 The contents of flag (F) register of 8086 indicate some conditions produced by
the execution of an arithmetic or logical instruction. It also contains some flag bits
to control the certain operations of the execution unit.
8086 Microprocessor Architecture
Explanations of 8086 Architecture
The 8086 internally divided into two separate functional units. These are the Bus
Interface Unit(BIU) and the Execution Unit (EU). These two functional units can
work simultaneously to increase system speed and hence the throughput.
Throughput is a measure of number of instructions executed per unit time.
Bus Interface Unit (BIU)
The bus interface unit is the 8086’s interface to the outside world.
 It provides a full 16 – bit bi – directional data bus and 20 – bit address bus.
 It is responsible for performing all external bus operations.
Functions:
 It sends address of the memory or I/O.
 It fetches instruction from memory.
 It reads data from port / memory.
 It writes data into port / memory.
 It supports instruction queuing.
 It provides the address relation facility.
To implement the above mentioned functions the BIU has the instruction queue,
segment registers instruction pointer, address summer and bus control logic.
Instruction Queue
To speed up program execution, the BIU fetches six instruction bytes ahead of time
from the memory. These prefetched instruction bytes are held for the execution unit in
a group of six registers called Queue.
 With the help of queue it is possible to fetch next instruction when current
instruction is in execution.
 The queue operates on the principle First In First Out (FIFO). So that the execution
unit gets the instructions for execution in the order they are fetched.
In case of JUMP and CALL instructions, instruction already fetched in queue are of
no use. Hence, in these cases queue is dumped and newly formed by loading
instructions from new address specified by JUMP or CALL instruction.
 Feature of fetching the next instruction while the current is executing is called
pipelining.
Execution Unit
 The Execution Unit of 8086 tells the BIU from where to fetch instructions or data,
decodes instructions and executes instructions. It Contains
Control Circuitry
 Directs the internal operations
Instruction Decoder
 It translates the instructions fetched from memory
ALU
 All Arithmetic and Logical Operations, INC, DEC
Flag Register
 Which indicates some condition produced by the
Execution of instruction or controls certain
operations of EU (Execution Unit)
General Purpose Registers
Pointers and Index Registers
Flag Registers
1.
Carry Flag : In case of addition this flag is set if there is a carry out of the MSB.
The carry flag also serves as a borrow flag for subtraction. In case of subtraction it
is set when borrow is needed.
2.
Parity Flag: It is set to 1 if result of byte operation or lower byte of the word
operation contain an even number of ones; otherwise it is zero.
3.
Auxiliary Carry : This flag is set if there is an overflow out of bit 3.
4.
Zero Flag: It sets if the result of operation in ALU is zero and flag resets if the
result is nonzero. The zero flag also set if a certain register content becomes zero
following an increment or decrement operation of that register.
5.
Sign Flag: After the execution of arithmetic or logical operations, if the MSB of
the result is 1, the sign bit is set. Sign bit 1 indicates the result is negative;
otherwise it is positive.
Flag Registers
6. Overflow Flag: This flag is set if result is out of range. For addition this flag is set
when there is a carry into the MSB and no carry out of the MSB or Vice – Versa.
For subtraction, it is set when the MSB, or Vice- Versa.
INTERNAL MICROPROCESSOR
ARCHITECTURE



Before a program is written or instruction investigated,
internal configuration of the microprocessor must be
known.
In a multiple core microprocessor each core contains the
same programming model.
Each core runs a separate task or thread simultaneously.
A thread consists of a program counter, a register set, and a
stack space.
A task shares with peer threads its code section, data section,
and operating system resources
The Programming Model

8086 through Core2 considered program visible.
 registers
are used during programming and are specified by
the instructions

Other registers considered to be program invisible.
 not
addressable directly during applications programming

80286 and above contain program-invisible registers to
control and operate protected memory.
 and



other features of the microprocessor
80386 through Core2 microprocessors contain full 32-bit
internal architectures.
8086 through the 80286 are fully upward-compatible
to the 80386 through Core2.
Figure 2–1 illustrates the programming model 8086
through Core2 microprocessor.
 including
the 64-bit extensions
Figure 2–1 The programming model of the 8086 through the Core2
microprocessor including the 64-bit extensions.
Multipurpose Registers



RAX - a 64-bit register (RAX), a 32-bit register
(accumulator) (EAX), a 16-bit register (AX), or as either
of two 8-bit registers (AH and AL).
The accumulator is used for instructions such as
multiplication, division, and some of the adjustment
instructions.
Intel plans to expand the address bus to 52 bits to
address 4P (252~1015 =peta) bytes of memory.
Address Space (Main Memory: RAM)





Address bus:16 bit Address Space:64 KBytes
Address bus:20 bit Address Space:1 MBytes
Address bus:32 bit Address Space:4 GBytes
Address bus:34 bit Address Space:16GBytes
Address bus:36 bit Address Space:64GBytes
Address bus:38 bit Address Space:256GBytes
Address bus:52 bit Address Space:1015 Bytes

RBX, addressable as RBX, EBX, BX, BH, BL.
 BX
register (base index) sometimes holds offset address
of a location in the memory system in all versions of the
microprocessor

RCX, as RCX, ECX, CX, CH, or CL.
a
(count) general-purpose register that also holds the
count for various instructions

RDX, as RDX, EDX, DX, DH, or DL.
a
(data) general-purpose register
 holds a part of the result from a multiplication
or part of dividend before a division

RBP, as RBP, EBP, or BP.
 points
to a memory
for memory data transfers

(base
pointer)
location
RDI addressable as RDI, EDI, or DI.
 often
addresses (destination index) string destination data
for the string instructions

RSI used as RSI, ESI, or SI.
 the
(source index) register addresses source string data for
the string instructions
 like
RDI, RSI also functions as a generalpurpose register

R8 - R15 found in the Pentium 4 and Core2 if 64-bit
extensions are enabled.
 data
are addressed as 64-,
sizes and are of general purpose

32-,
16-,
or
8-bit
Most applications will not use these registers until 64-bit
processors are common.
 the
8-bit portion is the rightmost 8-bit only
 bits
8 to 15 are not directly addressable
a byte
as
Special-Purpose Registers

Include RIP, RSP, and RFLAGS
 segment

RIP addresses the next instruction in a section of
memory.
 defined

registers include CS, DS, ES, SS, FS, and GS
as (instruction pointer) a code segment
RSP addresses
the stack.
 the
an
area
of
memory
(stack pointer) stores data through this pointer
called




RFLAGS indicate the condition of the microprocessor and
control its operation.
Figure 2–2 shows the flag registers of all versions of the
microprocessor.
Flags are upward-compatible from the 8086/8088
through Core2 .
The rightmost five and the overflow flag are changed by
most arithmetic and logic operations.
 although
data transfers do not affect them
Figure 2–2 The EFLAG and FLAG register counts for the entire 8086 and Pentium
microprocessor family.
• Flags never change for any data transfer or
program control operation.
• Some of the flags are also used to control
features found in the microprocessor.


Flag bits, with a brief description of function.
C (carry) holds the carry after addition or borrow after
subtraction.
 also

indicates error conditions
P (parity) is the count of ones in a number expressed as
even or odd. Logic 0 for odd parity; logic 1 for even
parity.
 if
a number contains three binary one bits, it has odd parity
 if a number contains no one bits, it has even parity
List of Each Flag bit, with a brief
description of function.

C (carry) holds the carry after addition or borrow after
subtraction.
 also

indicates error conditions
P (parity) is the count of ones in a number expressed as
even or odd. Logic 0 for odd parity; logic 1 for even
parity.
 if
a number contains three binary one bits, it has odd parity;
If
a
number
contains
no
one
bits,
it
has even parity




A (auxiliary carry) holds the carry (half-carry) after
addition or the borrow after subtraction between bit
positions 3 and 4 of the result.
Z (zero) shows that the result of an arithmetic or logic
operation is zero.
S (sign) flag holds the arithmetic sign of the result after
an arithmetic or logic instruction executes.
T (trap) The trap flag enables trapping through an onchip debugging feature.



I (interrupt) controls operation of the INTR (interrupt
request) input pin.
D (direction)
selects increment or decrement mode
for the DI and/or SI registers.
O (overflow)
occurs when signed numbers are added
or subtracted.
 an
overflow indicates the
the capacity of the machine
result
has
exceeded




IOPL
used
in
protected
mode
operation
to select the privilege level for I/O devices.
NT (nested task)
flag indicates the current task is
nested within another task in protected mode operation.
RF (resume)
used with debugging to control
resumption of execution after the next instruction.
VM (virtual mode) flag bit selects virtual mode
operation in a protected mode system.



AC, (alignment check) flag bit activates if a word or
doubleword is addressed on a non-word or nondoubleword boundary.
VIF is a copy of the interrupt flag bit available to the
Pentium 4–(virtual interrupt)
VIP (virtual) provides information about a virtual mode
interrupt for (interrupt pending) Pentium.
 used
flags
in multitasking environments to provide virtual interrupt

ID (identification) flag indicates that the Pentium
microprocessors support the CPUID instruction.
 CPUID
instruction provides the system with information about
the Pentium microprocessor
Segment Registers




Generate memory addresses when combined with other
registers in the microprocessor.
Four or six segment registers in various versions of the
microprocessor.
A segment register functions differently in real mode
than in protected mode.
Following is a list of each segment register, along with its
function in the system.


CS (code) segment holds code (programs
procedures) used by the microprocessor.
DS (data) contains most data used by a program.
and
 Data
are accessed by an offset address or contents of other
registers that hold the offset address

ES (extra) an additional data segment used by some
instructions to hold destination data.

SS (stack) defines the area of memory used for the
stack.
 stack
entry point is determined by the stack segment and
stack pointer registers
 the
BP
register
also
addresses
data
within
the stack segment

FS and GS segments are supplemental segment
registers
available
in
80386–Core2
microprocessors.
 allow
two additional
access by programs

memory
segments
for
Windows uses these segments for internal
operations, but no definition of their usage
is available.