HW/SW Co-Verification
By: Getao Liang
March, 2006
-- Mentor Graphics® Seamless CVE
LOGO
Contents
1. HW/SW Co-Verification
2. Seamless CVE
3. CVE Tutorial
4. Conclusions
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Introduction
Embedded System & SoC
 Hardware
•
•
•
•
Processor (s)
Memory Blocks
IP Blocks
Bus
 Software
• Communication with CPU and I/O
• Memory Access
 HW/SW Integration
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Traditional Design Cycle
1. High-Level
Design
2. Detail &
Implementation
•Requirement
Analysis
Hardware
Design &
Simulation
Hardware
Prototyping
Software
Design
HW/SW
Integration
•Sub-systems
3. Physical
Integration
•High-Level
Simulation
•HW/SW
Interface
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Motivation
Time to Market
 Shorten Time-to-Market = ?
• Save Resource
• More Profit
• Market Domination
Advance Verification
 Lower Cost to Problem Correction
 Easier Debugging
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Comparison
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HW/SW Co-Verification Model
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Co-verification Vs. Simulation
RTL Simulation
 Pure RTL models
 Slow: <100Hz
 Unable to address all debug requirement
Co-Verification
 Orders of Magnitude Faster
 Increased Comprehension
 Support for Abstract Models
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Contents
1. HW/SW Co-Verification
2. Seamless CVE
3. CVE Tutorial
4. Conclusions
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Mentor Graphics ® Seamless CVE
Interactive Debugging Tool
Bus
Interface
Model
Memory
Models
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Key Concepts of CVE
Accelerating Co-Verification Process
 Separate Processor’s Functions
 Suppress Bus Cycles Selectively
Important Components
 Processor Support Packages (PSP)
• Instruction Set Model (ISM) - SW
• Bus-Interface Model - HW
 Memory System
• Optimizable Memory Models
• Coherent Memory Server (CMS)
 Coherent Timers
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Processor Support Packages
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Instruction Set Model
•Software Model
•Functional Behavior of
Processor’s Instruction Set
•Abstract Model of Data
Processing
•Instruction Set Simulation - IIS
- Running ISM on a software
simulator.
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Bus-Interface Model
•Hardware Model
•Input/Output Pin Behavior
of Processor
•No Internal Logic of
Processors
•Bus Activities
•R/W Memory
•R/W I/Os
•R-modify-W
•Reset and Halt
•.Interrupts, Faults
•Bus Request & Grant
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Software Co-Verification
SW
Design
Loading
Test
Design software
with crosslanguage tools
to generate
machine code
for target
processor.
Introduce
Seamless
application into
design flow, and
load executable
software
modules into
ISM address
space of the
processor.
The Seamless
kernel handles
communication
s between the
ISM and Businterface model
in hardware
part.
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Optimizable Memory Models
•Generic Optimizable Memory
Models
– Supplied with Seamless as
HDL files. (for simple memory
blocks, like dRAM, sRAM, DPRAM, FIFO, Register Memory.)
•Denali Memory Models
– Created with PureView
application. (for commercial
memory devices)
•Seamless HDL Memory
Interface
– Converted from existing
models to Seamless optimizable
models
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Optimizable Memory Models (Cont’l)
 Generic Memory Models
 $CVE_HOME/vsim_vdl
 $CVE_HOME/vlog
 Denali Memory Models
 Obtain a SOMA file
• http://www.ememory.com
 Generate HDL Memory Model
• PureView or MemMaker
 HDL Memory Interface
 Compile iram.vhd
 Add USE work.cve_direct.all;
 Modify with Seamless HDL memory interface calls
• cve_RegisterMemory()
• cve_ReadMemory()
• cve_WriteMemory()
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Optimization
Why
 Accuracy vs. Performance
What
 Frequently accessed memory
How
 Direct Access (bus cycles hiding)
 By Coherent Memory Server
CMS
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Optimization Categories
Data Access
Optimization
Instruction Fetch
Optimization
 Disables hardware
bus cycles when
accessing optimizable
memory
 Eliminates all bus
activities for instruction
fetches from
optimizable memory
 Decouples time
synchronization
between HW and SW
 Functional Accurate
Cycle Accurate
 Functional Accurate
Cycle Accurate
 Functional Accurate
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Time
Optimization
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Full Activity Simulation
Simulation Bus
Activity
• Instruction Fetch
• Memory Read/Write
• I/O Read/Write
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Optimized Simulation
Simulation Bus
Activity
• Instruction Fetch
• Memory Read/Write
• I/O Read/Write
• Memory Write to UNOPTIMIZABLE Address
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Increased Performance
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Seamless Coherent Timers
Maintain an accurate count of clock cycles
when running in time-optimized mode.
Be programmed to make logic simulator to
service timer events appropriately.
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Contents
1. HW/SW Co-Verification
2. Seamless CVE
3. CVE Tutorial
4. Conclusions
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Basic Steps
Hardware Design
 Replace processor modules with
corresponding bus-interface Models
 Modify memory modules
Software Design
 Machine code for target processor
 Software for Host Code Execution (HCE)
CVE Invocation
 Logic and SW simulators configuration
 Memory mapping
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Demo Design
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Demo Tutorial
 Setup Environment
 Compile Software
 Invoke Seamless
 Invoke Logic Simulator - ModelSim VHDL
 Configure the Processor - DLX
 Setup SW simulator/debugger – MDB
 Map memory instances
 Define memory access detail
 Start Co-verification Session
 Enable Data Access Optimization
 Enable Time Optimization
 Enable Instruction Fetch Optimization
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Contents
1. HW/SW Co-Verification
2. Seamless CVE
3. CVE Tutorial
4. Conclusions
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THE UNIVERSITY OF TENNESSEE
Conclusions
Early Integration
 Shorten time-to-market
 Lower cost for verification and correction
Easy Debugging
 Control SW execution
 View/Change memory contents
Enhancing Performance
 ISM + BIM
 CMS + Optimizable Memory
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References
 Mentor Graphics,
Seamless Reference Manuals
 Milan Saini,
Co-Verification Enhances Time to Market Advantage of Platform
FPGAs
 Mike Andrews,
Seamless-izing Memories for Seamless Hardware/Software
 J. M. Ng,
Enhancing HW/SW Co-Verification for Embedded System with
Seamless
 CIC [email protected],
HW/SW Co-Verification using Mentor Graphics Seamless CVE: A
Case Study with AUK system
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Liang, Getao – gliang (at) utk (dot) edu
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