Pattern Sensitive Placement For
Manufacturability
Shiyan Hu, Jiang Hu
Department of Electrical and Computer Engineering
Texas A&M University
College Station, TX, 77843
Outline






Lithography system
Motivation
Problem formulation
Algorithms
Experimental results
Conclusion
2
Lithography Process
optical
mask
Part of layout
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
spin, rinse, dry
3
Lithography System
Illumination
193nm
wavelength
Source
Mask
45nm
features
Objective Lens
Wafer
4
Motivation

Printability problem
– Lithography technology: 193nm wavelength
– VLSI technology: 45nm features
– Lithography induced variations
 Impact on timing and power
– Even for 180nm technology, variations up to 20x in
leakage power and 30% in frequency were reported.
Technology node
130nm
90nm
65nm 45nm
Gate length (nm)
Tolerable variation (nm)
90
5.3
53
3.75
35
2.5
28
2
Wavelength (nm)
248
193
193
193
5
Lithography Tech. v.s. VLSI Tech.
193nm
28nm, tolerable
distortion: 2nm
6
Improve Printability by RET
Resolution
Enhancement Technique (RET)
–Post Physical Layout Design
–Weakness:
Limited
capacity and increasingly difficult
Expensive mask cost
OPC
7
Design For Manufacturability (DFM)


Efforts are needed in all design and
process stages.
Physical design considering printability:
Design For Manufacturability (DFM).
– To make RET easier and cheaper to
apply
8
Previous Works on DFM


Regular fabric:
– Introduce regular geometry, similar to FPGA
– Compromised performance
Restricted design rules:
– Not able to accurately capture lithography effects
– Rule explosion: 2000 pages in 22nm technology
(From DAC’05)
9
Previous Works on DFM



Regular fabric:
– Introduce regular geometry, similar to FPGA
– Compromised performance
Restricted design rules:
– Not able to accurately capture lithography effects
– Rule explosion: 2000 pages in 22nm technology
RET-friendly detailed placement (ASPDAC’05):
– Small spacing perturbation
– No cell flipping, no cell relocation
Our Problem


Physical layout design considering manufacturability
Cell Placement
– Given a circuit, decide the physical location of each gate
– A major step in the physical layout design flow
– Objectives: small wirelength, small area, good timing, etc.
Placement
11
This Work

Post-placement optimization for printability
– Post-placement optimization
 Applicable
to any existing placement to make
it easier to print
 Limit modification to retain benefits
– Improve printability
 Measurement of printability
 How?
– Relocation and Flipping
12
Measurement of Printability

Manufacturability cost
– Edge Placement Error (EPE), Image Log Slope
(ILS), process window,…
: EPE
13
From http://www.vlsitechnology.org/
Relocation and Flipping
Existing Placer
Hard to
print by
simulation
Our Optimization
Easy to
print by
simulation
14
Cell Flipping to Improve Printability
50% reduction
in gate length
deviation
15
From http://www.vlsitechnology.org/
Our Approach

Offline:
– For each possible
pattern formed by
two cells, assign a
manufacturability
cost
Pattern: part between
horizontally adjacent cell pair
 Accurate
lithography
simulations
 Results saved in
a lookup table

Online:
– Prefer easy-to-print
patterns in design
From http://www.vlsitechnology.org/
16
Problem Formulation



Given a cell placement
Perform post-processing optimizations, which
can be cell flipping and relocation
Total manufacturability cost (sum of
manufacturability cost over all patterns) is
reduced subject to the modification (wire
length) constraint.
17
Optimization Considering Cell Flipping
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

The algorithm is for row-based layout.
Perform optimization row by row.
For each row of cells, perform the dynamic
programming style optimization.
18
Optimizing A Row by Cell Flipping
1
2
After processing the last
cell, pick the solution with
best manufacturability cost
while satisfying wirelength
constraint
19
Solution Characterization and
Update

Each candidate solution is associated with
– c: a cell
– CE: cumulative manufacturability cost
– CW: cumulative wire length

c is being processed,
– CE  CE + manufacturability cost of new pattern
– CW  HPWL on all nets not spanning on any
unprocessed cell.
c
20
Solution Pruning

Two candidate solutions
– Solution 1: (c, CE1, CW1)
– Solution 2: (c, CE2, CW2)

Solution 1 is inferior if
– CE1 > CE2 : larger cumulative manufacturability cost
– and CW1 > CW2 : larger cumulative wirelength

Whenever a solution becomes inferior, it is pruned.
21
Single Row Optimization



Allow both cell flipping and cell relocation.
Partition a row of cells into groups.
Small modification  a cell movable only within a group.
22
Flow for Single Row Optimization
Partition a row of cells into groups
Pick groups for optimization
Difficult
Perform group optimization tentatively
Accept the result if printability is improved
and overhead satisfies constraint
23
Group Optimization
Difficult
Compute the placement with best manufacturability
cost (no wirelength constraint)
Compute the placement with best wirelength (initial
placement)
Difficult
Tradeoff: gradually tune best manufacturability
placement towards the best wirelength placement
24
Placement with Best Manufacturability Cost
:0
: manufacturability cost
25
Placement with Best Manufacturability Cost
:0
: manufacturability cost
26
Placement with Best Manufacturability Cost
:0
: manufacturability cost
27
Placement with Best Manufacturability Cost
:0
: manufacturability cost
Flipped
28
Placement with Best Manufacturability Cost
:0
: manufacturability cost
29
Placement with Best Manufacturability Cost
:0
: manufacturability cost
Every placement
corresponds to a
Hamiltonian path
30
Minimum Cost Hamiltonian Path Problem

The placement with best manufacturability cost 
the minimum cost Hamiltonian Path
– No wirelength constraint


Well-known NP-hard problem
Closest point heuristic is used
31
Handle Wirelength Constraint
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
Start from best manufacturability solution
Gradually adjust it to satisfy wirelength constraint
Best Manufacturability
A
B
C
D
E
Best Wire
B
A
E
D
C
Reduce crossings: fewer crossings  closer to best
wire solution  possible to satisfy the wirelength
constraint
Handle Wirelength Constraint


Start from best manufacturability solution
Gradually adjust it to satisfy wirelength constraint
Best Manufacturability
A
B
C
D
E
Best Wire
B
A
E
D
C
Handle Wirelength Constraint


Start from best manufacturability solution
Gradually adjust it to satisfy wirelength constraint
Best Wire

A
B
E
D
C
B
A
E
D
C
Able to get the solution with good manufacturability
cost satisfying the wirelength constraint
Multiple Row Based Optimization

Motivation
– A net often spans adjacent rows
– Moving cells in different rows simultaneously may
reduce wirelength
– Some previously “infeasible” manufacturability-driven
placement may become “feasible”. More options.

Feasible: satisfy wirelength constraint
– Improved manufacturability cost
35
Experiments

Experiment Setup
– ISCAS’ 89 (>10K cells in a circuit) and ISPD’ 04
benchmark (>200K cells in a circuit)
– 130nm technology
– SPLAT for lithography simulation
– 1% wire length increase bound
– Lookup table size: <1M
– Lookup table access time: <0.1ɥs per entry
– A Pentium 4 machine with a 3.0GHz CPU 2G
memory
36
ISCAS’89: EPE reduction %
Cell Flipping
Single Row Optimization
Multiple Row Optimization
25
20
15
10
5
s9
23
4
s1
58
50
s3
59
32
s3
84
17
s3
85
84
s1
48
8
s5
37
8
s1
23
8
s1
42
3
0
s8
38
EPE Reduction %
30
37
ISCAS’89: Wirelength Increase %
Single Row Optimization
Multiple Row Optimization
s9
23
4
s1
58
50
s3
59
32
s3
84
17
s3
85
84
s1
48
8
s5
37
8
s1
23
8
s1
42
3
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
s8
38
Wirelength Increase
%
Cell Flipping
38
ISCAS’89: Runtime (seconds)
Single Row Optimization
Multiple Row Optimization
s9
23
4
s1
58
50
s3
59
32
s3
84
17
s3
85
84
s1
48
8
s5
37
8
s1
23
8
s1
42
3
100
90
80
70
60
50
40
30
20
10
0
s8
38
CPU (s)
Cell Flipping
39
Observations
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Cell Flipping:
– 9% EPE reduction
– 0.17% additional wire
– Fastest

Single Row Optimization:
– 14.6% EPE reduction
– 0.35% additional wire
– 2x slower compared to Cell Flipping

Multiple Row Optimization
– 22% EPE reduction
– 0.57% additional wire
– 4x slower compared to Cell Flipping
40
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EPE Reduction %
ISPD’04: EPE Reduction %
Cell Flipping
Single Row Optimization
Multiple Row Optimization
35
30
25
20
15
10
5
0
41
ISPD’04: Wirelength Increase %
Percentage
Cell Flipping
Single Row Optimization
Multiple Row Optimization
0.8
0.7
0.5
0.4
0.3
0.2
0.1
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Wirelength Increase %
0.6
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ISPD’04: CPU (s)
Cell Flipping
Single Row Optimization
Multiple Row Optimization
6000
5000
3000
2000
1000
0
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CPU (s)
4000
Observations
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Cell Flipping:
– 11% EPE reduction
– 0.16% additional wire
– Very fast

Single Row Optimization:
– 18% EPE reduction
– 0.29% additional wire
– 50% slower

Multiple Row Optimization:
– 25% EPE reduction
– 0.41% additional wire
– 2x slower
44
Conclusion

Propose three algorithms for pattern sensitive
placement for manufacturability:
– Cell Flipping only
– Single Row Optimization
– Multiple Row Optimization

>20% edge placement error reduction.

<1% wire length overhead.

Runtime acceptable for large placement
benchmark.
45
46