Name (First and Last): ________________________
CS2630:ComputerOrganization
Finalexam
December14,2016
The exam is open book/open note. No electronics. Show your work when appropriate.
Take a deep breath… and relax.
Question
0
1
2
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TOTAL
Points
/1
/9
/ 12
/ 21
/8
/ 51
Question0(1point)
a) write your name on every piece of paper where it says “Name (First and last)”
(graded for correctness)
b) draw a mark on this spectrum (graded for participation)
Do not open the test before given permission
THIS PAGE INTENTIONALLY LEFT BLANK
Name (First and Last):____________________
1. Misc(9points)
a) How many things can you name uniquely with M bits? __________
b) True / False: Programs can be stored in memory.
c) True / False: MIPS is a microarchitecture.
d) True / False: The digital abstraction provides a simple 0’s and 1’s interface
between components.
e) True / False: Digital logic is only used for building CPUs.
f) True / False: MIPS processors must have exactly one arithmetic logic unit (ALU)
g) Suppose we want to copy the value in register $t1 into register $s1. Circle the
one MIPS instruction that does that.
A. or
$s1, $s1, $t1
B. sub $s1, $t1, $zero
C. add $s1, $t1, $t1
D. and $s1, $t1, $zero
E. none of the above
h) Suppose we improved the design of the cache and increased its hit ratio. For
each of the three factors of processor performance, say whether the factor will
INCREASE, DECREASE, or NO CHANGE as a result of the higher cache hit
ratio.
Instructions per cycle
i)
cycles per second
instructions per program
Which of the following would reduce the cost of an associative lookup in the
cache? (circle all that apply).
A. Decrease the number of rows in the cache (capacity decreases)
B. Increase the number of rows in the cache (capacity increases)
C. Decrease the number of places a given cache line could go (associativity
decreases)
D. Increase the number of places a given cache line could go (associativity
increases)
2.MIPSProcessorTesting(12points)
D
A
E
B
C
Your coworker wrote a short program to try to use each input of every MUX in the
above datapath at least once. They may or may not have finished the task.
a) (10 points) To find out whether the program uses all the MUX inputs or not, you
must fill in the below table.
• The MUXs are labeled above. In the A,B,C,D,E columns write a 0 or 1 to indicate
for that instruction which input to the MUX was selected.
• If the MUX’s output is not used by the instruction, leave the cell blank.
• If the instruction is never executed, then leave all its columns blank.
label
Instruction
A
B
C
D
E
add $t0, $zero, $zero
beq $t0, $zero, fuz
addi $t0, $t0, 1
fuz:
j cat
addi $t0, $t0, 1
cat:
addi $t0, $t0, -1
b) (2 points) Did the program use all inputs of every MUX (yes/no)? _____________. If
“no”, then add one more instruction that will complete the test program.
Name (First and Last):____________________
3. MIPSprocessorimplementation(21points)
Compiler engineers at your company noticed that it is very common to have code that
loops through an array, where the size of the array elements is 4 bytes.
To make programs run faster, they’ve asked you to add a new instruction to the MIPS
instruction set architecture called lwa (load word from array).
The instruction syntax is as follows:
lwa $rd, $rs, $rt
The specification for the instruction in register transfer language (RTL) is:
R[rd] = M[ R[rs] + (R[rt] * 4) ]
a) (3 points) Consider a specific instance of the lwa instruction:
lwa $s1, $t1, $a1
Fill in the instruction format, using hexadecimal for each field. It is your job to pick an
appropriate opcode and funct, too.
opcode
$rs
$rt
$rd
shamt
funct
b) (6 points) Add the necessary circuitry to the datapath diagram to support lwa. You
are allowed to use whatever basic components you need (gates, adders, shifters,
muxes, comparators, etc). Write in the names of any new control signals in blank
space within the Control Unit. You must keep it simple, draw legibly, not be
ambiguous, and make wires have right angles.
c) (6 points) Fill in the values of the control signals for the lwa instruction. They must
match your datapath above.
• The choices for ExtOp are SIGN or ZERO.
• The choices for ALUCtr are the names of operations such as ADD, SUB,
SLL, SRL, etc.
• There are two optional blank columns for your own control signals.
RegDst
ExtOp
RegWrite
ALUSrc
ALUCtr
MemWr
MemTo
Reg
Branch
Jump
Name (First and Last):____________________
d) (6 points) You must test your processor with the new instruction. We would like to
write a MIPS program that uses the lwa instruction.
The lwa syntax and RTL are repeated here for your convenience.
lwa $rd, $rs, $rt
R[rd] = M[ R[rs] + (R[rt] * 4) ]
Here is the test program written in Java. Your job is to translate the program to MIPS.
Assume arr is an int[ ]
(i.e., array of integers).
int sum = 0;
for (int i=0; i<Y; i++) {
s += arr[i];
}
Your coworker got the MIPS version started for you. Fill in the remaining blanks (there
are 2 blanks for instruction arguments and 2 blanks for instructions).
# assumes the value of Y is already in $s0
# assumes address of the beginning of arr is already in $s1
snow:
rain:
Optionally, use this column for comments
addi $s2, $zero, 0
# initialize sum
addi $t0, $zero, 0
#
bge ____, ____, rain
#
___________________________ #
___________________________ #
addi $t0, $t0, 1
#
j snow
#
# end of program
4. Digitallogic(8points)
a) (4 points) Consider the following circuit
And the component attributes
CLK-to-Q
setup time
delay of adder
delay of subtractor
W picoseconds
X picoseconds
Y picoseconds
Z picoseconds
What is the maximum clock frequency we can run this circuit at? (include the units in
your answer)
Name (First and Last):____________________
b) (4 points) Describe the output Out in terms of the input In. Your answer may be
in the form of either (but not both):
• One short English sentence
• A state transition diagram