CSCI206 - Computer Organization &
Programming
Logical Operations, Making Decisions
zyBook: 5.6, 5.7
Developed and maintained by the Bucknell University Computer Science Department - 2017
MIPS Integer Operations
Bitwise/logical Instructions
Category
Instruction
C operator
MIPS Instruction
Logical
shift left
<<
sll
shift right
>>
srl
bitwise AND
&
and, andi
bitwise OR
|
or, ori
bitwise XOR
^
xor, xori
Shift Left - Machine Code
r-type instruction with an immediate!
sll $s1, $s0, 8
shift left
16
17
0
opcode
8
rs
rt
rd
shift amount
0
function
unused (0)
0x00108A00
R[rd] = R[rt] << shamt
Comparison and Decision Instructions
slt rd, rs, rt
;set less than: R[rd] = (R[rs] < R[rt]) ? 1 : 0
slti rt, rs, imm ;set less than immediate
;R[rt] = (R[rs] < imm) ? 1 : 0
beq r1, r2, label ; branch to label if r1 == r2
bne r1, r2, label ; branch to label if r1 != r2
Common Programming Patterns
Decisions
Loops
if (boolean condition){
(consequent)
}else{
(alternative)
}
do{
switch (var){
case 0: //case_0_code;
break;
case 1: //case_1_code;
break;
case 2: //case_2_code;
break;
default: //default_code;
break;
}
// Code for the loop's body
// goes here.
}while(condition)
while(CONDITION){
// Code for the loop's body
// goes here.
}
for(INITIALIZATION; CONDITION; UPDATE){
// Code for the for loop's body
// goes here.
}
IF
// assume a is an int
if (a == 1) {
// consequent code
}else{
// alternative code
}
lw
$t1, 0($s0)
;load a from mem
addi $t2, $zero, 1 ;set $t2 to 1
IF: beq $t1, $t2, A
; alternative code
j ENDIF
A:
; consequent code
ENDIF:
lw
$t1, 0($s0)
;load a from mem
addi $t2, $zero, 1 ;set $t2 to 1
IF: bnq $t1, $t2, B
; consequent code
j ENDIF
B:
; alternative code
ENDIF:
If activity
if ($a0 > 127){
$v0 = 1;
} else {
$v1 = 1;
}
If solution
if ($a0 > 127){
$v0 = 1;
} else {
$v0 = 0;
}
DO/WHILE
x = 15;
do{
// Code for the loop’s body
// goes here.
x = x - 1
} while(x >= 10)
addi $t0, $zero, 15
do_begin:
; Loop body
addi $t0, $t0, -1
slti $t1, $t0, 10
beq
$t1, $zero, do_begin
do_end:
WHILE/DO
x = 15
while(x >=
// Code
// goes
x = x }
10){
for the loop’s body
here.
1
addi $t0, $zero, 15
while_begin:
slti $t1, $t0, 10
beq
$t1, $zero, while_end
; LOOP BODY
addi $t0, $t0, -1
j while_begin
while_end:
While activity
$v0 =
while
$v0
$a0
}
0;
($a0 > 0){
^= 1;
= $a0 & ($a0 - 1);
While solution
$v0 =
while
$v0
$a0
}
0;
($a0 > 0){
^= 1;
= $a0 & ($a0 - 1);
FOR
for(i = 0; i < 10; i ++){
// Code for the for loop's body
// goes here.
}
addi $t0, $zero, 0
for_begin:
slti $t1, $t0, 10
beq $t1, $zero, for_end
; LOOP BODY
addi $t0, $t0, -1
j for_begin
for_end:
For activity
$v0 = 0;
for ( $t0 = 0; $t0 < 32; $t0++ ){
if ( ($a0 >> $t0) & 0x1 == 0x1 ){
$v0 ^= 1;
}
}
For solution
SWITCH
switch (var){
case 0: //case_0_code;
break;
case 1: //case_1_code;
break;
case 2: //case_2_code;
break;
default: //default_code;
break;
}
BEQ var, 0, CASE_0
BEQ var, 1, CASE_1
BEQ var, 2, CASE_2
default:
; default_code
j END
CASE_0:
; case_0_code
j END
CASE_1:
; case_1_code
j END
CASE_2:
; case_2_code
j END
END:
SWITCH (jump table)
switch (var){
case 0: //case_0_code;
break;
case 1: //case_1_code;
break;
case 2: //case_2_code;
break;
}
.data
TABLE:
.text
sll
lw
jr
.word CASE_0
.word CASE_1
.word CASE_2
$t1, var, 2
$t0, TABLE($t1)
$t0
CASE_0:
; case_0_code
j END
CASE_1:
; case_1_code
j END
CASE_2:
Warning: this assumes all cases are
used (starting with zero) and the input
is valid!
; case_2_code
j END
END:
Pseudo branch instructions
The assembler uses the $at register and slt
to implement
blt (branch less than)
bgt (branch greater than)
ble (branch less than or equal)
bge (branch greater than or equal)
Pseudo Branch Example
blt $t0, $t1, label
slt $at, $t0, $t1
bne $at, $zero, label
true-instruction
pseudo-instruction
if $t0 < $t1
j label
if $t0 < $t1
$at = 1;
else
$at = 0;
if $at != 0
j label