High-Speed
Serial Interface Test
in Production
Assure Device Interoperability In
Real-World Environments
About GuideTech
 Specializing in Precision Timing for Semiconductor Test and
Scientific Lab Communities since 1988
 Core Technologies
 Continuous Time Interval Analyzer (CTIA)
 Fast Datacom Analysis Software (DCA)
 High Channel Count, Parallel Architecture
Targeting production test of
high-speed serial interfaces
Sample Applications
Semiconductor Test
 PLL & Spread Spectrum Clocks
 Source Synchronous Bus
 Embedded-Clock Serial I/O
ASE test floor
Scientific Analysis
 Jet Engine Rotation/Vibration
 Atomic Clock Drift & Particle decay
 GuideTech Keeps the Planet’s time!
US Master Clock at the US Naval Observatory
The Need for Speed
 PCs move to high-speed serial buses in 20051
 80% - 2.5Gbps PCI-Express
 100% - 1.5Gbps Serial-ATA
 20% - Gigabit Ethernet
 But test quality is not yet assured!
2 pairs of differential channels @ >800Mbps
16 channels @ < 200Mbps
Controller
Device
1 Morgan
Stanley – Sep 22, 2003 Semiconductor Capital Equipment Industry Research
Controller
Device
ATE Performance Gap
1.2G - 3.2G
Embedded-clock Serial
(e.g. XAUI, SATA, FC
& PCI-Express)
Performance
1.6G
Source Synchronous
Flat Panel DVI Digital
Video Interface
GuideTech has been
filling the gap
since 2001
High Speed
High Accuracy
High Throughput
Asynchronous test
DUT
400MHz
+/-150ps
Digital
Synchronous
ATE
Spread Spectrum PLL
Clocks
To lower EMI emissions of
cell phones & consumer
devices
2001
2004 Year
A New Test Paradigm
Scope
CTIA & DCA
• Slow, Statistical Averaging
• Gross test of Total Jitter & Eye
• Fast, Frequency Domain Analysis
• Per-edge timing analysis
Continuous TIA Technology
 Continuous Timestamps
 Record edge timing & event count relative to (T0,E0)
 Multiple measurement types derived from same data set
 All measurement channels reference same (T0,E0)
 Powerful Pulse Selection Arming
 “Walk” measurements through data patterns
 Skip pulses to measure specific pulses
E0
E1
T0
T1
E2
T2
T3
E3
T4 T5
T6
CTIA Local Memory
Meas #
1
2
3
Event #
E1
E2
E3
Timestamps
T1 , T2
T3 , T4
T5 , T6
Real-Time DSP
PWE2
Meas #
1
2
3
Event #
E1
E2
E3
Pulse Width
T2 – T1
T4 – T3
T6 – T5
Non-Continuous TIA Drawbacks
 Non-Continuous TIA based on simple Time Counter technology
 Random, absolute measure of time intervals
 No inherent reference to common (T0,E0)
 Relies heavily on Statistical Analysis methods
Time interval #1
Time Interval #2
 Requires physical Pattern Marker for highest accuracy
 Pattern match adds test time to synchronize to patterns
 Pattern match unreliable in presence of large jitter
 Requires repeating SEARCH for one-shot measurements
 PLL Lock Time
CTIA Single-Shot Capability
 Test PLL & Spread Spectrum Clocks in production
 One-shot
 Frequency
 Modulation
 Lock Time
 Jitter
 No arming
 Picosecond accuracy
 In milliseconds
 8 in parallel
 Up to 64 channels
CTIA Frequency Domain Analysis
 CTIA time correlation enables plot of time interval error (TIE)
Dt 0
TIE Dt
Dt 1
Dt 2
(ps)
Dt 3
Dt 4
Dt 5
Dt 6
Auto Correlation Plot
Of Sinusoidal Jitter
Time (us)
FFT of the TIE plot provides
the amplitude and frequency of
sinusoidal jitter/modulation
AMPLITUDE
fjitter
FREQ
Functional Test of
Non-deterministic Signals
ATE Digital Compare Method – Requires Match Mode to position strobes
11
00 1 0 0
1 1 0 0 1 0 0
1 1 0 0 1 0 0
Match
1 1 0 0 1 0 0
1 1 0 0 1 0 0
1 1 0 0 1 0 0
1 1 0 0 1 0 0
Non-continuous TIA – Requires Marker to locate desired bit location
11
00 1 0 0
11
00 1 0 0
11
Pattern Marker
11
00 1 0 0
Match
00 1 0 0
11
00 1 0 0
PM selects the next desired pulse to measure
Continuous TIA – Reconstructs repeating signals with ‘Virtual Marker’
11
GT4000
T0
E0
00 1 0 0
11
T1
E2
00 1 0 0
11
T2
E5
00 1 0 0
11
T3
E7
00 1 0 0
CTIA “Virtual Marker”
 Edge isolation & reconstruction of non-deterministic bit patterns
 Known Bit Pattern & UI
 Selectable Bit Event Count
 Correlated CTIA Timestamps (Tn,En)
 More reliable than a physical pattern marker in high jitter signals
 Reduces test times to milliseconds for…
 Per-edge jitter analysis
 Asynchronous pattern verification
Serial Interface Test in Production
 Many test options




High-$peed ATE
BERT
Scope
Jitter Analyzers
 Few cost-effective approaches
 Loopback
 On-chip DFT/BIST
But ‘no test’ is not an option anymore…
Serial I/O Loopback Test
 Benefits
 Low-cost vs expensive ATE pin electronics
 Addresses asynchronous issue with ATE
TXdiff
RXdiff
 Drawbacks
 Gross Functional Test only
 Does not insure device interoperability in real-world
system environments
Assure Real-World Performance
 BER helps insure real-world performance but is too slow for production
 High-throughput jitter analysis can estimate BER in production
Far-end
Near-end
 TX Jitter Analysis
• Predicts far-end jitter degradation after TX signal is subjected to system
connectors, switches and PCB traces
TXdiff
CTIA measures TX jitter
in loopback path
RXdiff
Random Jitter
 Causes of Random Jitter
 Thermal noise
 Transistor current fluctuation ‘shot’ noise
 Flicker noise (1/f noise)
 Random Jitter is a contributing factor to Bit Error Rate
BER
10-6
10-8
SJ
DJ
10-10
QxRJ
Eye Width @
BER 10-12
10-12
Q = 14.069 @ BER 10-12
RJ is important for fast BER estimation
 Measuring Bit Error Rate on a BERT can take hours or days
 Quickly determine Total Jitter for a BER of 10-12
BER
Jitterp-p = ( Q x RJRMS ) + DJ
Q = 14.069 @ BER 10-12
10-12
QxRJ
 Due to the large Q multiplication factor, RJ measurements
must not be contaminated by PJ and DDJ components
Probability Density Functions (PDF) of jittering edge timing
Gaussian RJ
RJ contaminated by PJ
RJ contaminated by DDJ
Data-Dependent Jitter is Important
 Most PHY-layer I/O failures are DDJ-related
 Causes of DDJ
 Bandwidth limitations in signal path
• Frequency dependent
• Pattern dependent
 Output driver faults
 Duty cycle distortion
 Rise/fall times
 Packaging
CTIA DataCom Jitter Analysis
 GuideTech DCA Provides:
 Data Pattern Verification
 Random Jitter (RJ)
 Data-Dependent Jitter (DDJ)
 Periodic Jitter (PJ)
 Total Jitter (TJ)
 Bit Error Rate (BER)
 Eye Width
Continuous TIA technology enables
fast and accurate quality assurance
CTIA RJ Immune to PJ
 CTIA continuous timestamping enables
 Statistical (Curve fit) methods are prone to
isolation of the RJ noise floor by removal of
estimation errors depending on the PDF
PJ frequency components in the FFT
shape
spectrum and DDJ using virtual marker
Jitter Amplitude (UI)
Remove Spread Spectrum Clock
Modulation
1UI
Remove other periodic jitter
0.5UI
Remaining Noise Floor
(Random RMS Jitter)
0.1UI
0.1MHz
10MHz
50MHz
PDF showing
RJ contaminated by PJ & DDJ
RJ Immunity to DDJ
 CTIA continuous timestamps act as a
‘virtual’ marker
 Isolate edges
 Remove DDJ offset before
performing FFT for RJ analysis
0101 100000100
T0
IDEAL Edge-6 location
Count
DDJ offset
1P
1N
2P
2N
3P
3N
CTIA vs. ‘double-delta’ method
 CTIA measures edge shifts independently on each data bit
 Produces highly repeatable DDJ results per-edge
 Avoids inaccuracies of statistical double-delta methods*
P1
N1 P2 N2
P3
N3
P4
N4
P5
N5 P6
N6
Continuous TIA
Non-Continuous TIA
Inherent DDJ inaccuracies of double-delta method*
*Reference: Fibre Channel MJS document Section 12.2.2 & 12.2.7
10x Throughput with Picosecond
DCA Correlation to Scope
 DCA correlates to Agilent 86100 within picoseconds
 DCA test time is less than 1 sec vs. 10 sec on scope (K28.5)
DCA Fast Jitter Separation
 Select DCA test time




Pattern length
PJ resolution
PJ ON/OFF
RJ precision
Test PCI Express
in 1 second
(including pattern verify)
Test Time (sec)
PJ – ON (RJ, DDJ, PJ, TJ)
} PJ resolution
} RJ precision
10s
5s
1s
PJ – OFF (RJ, DDJ & TJ only)
250ms
K28.5
PCIe
640 bit
Compliance Pattern
PRBS15
32,767 bits
Pattern
Length
(bits)
The Value of Jitter Test
 Jitter test saves money
 Test Escapes
• Field Returns
• RMA failure analysis
• Lost Business
 Yield Loss
• Failing good devices
 Time-to-Market Delays
• Long characterization-to-production correlation time
• Unprepared to debug unexpected process variation at final test
CTIA Provides the Missing Pieces
 Test Asynchronous signals
Introducing the
GT4000
 High Throughput “Virtual Marker”
 Repeatable Jitter Analysis
 64 Single-ended / 32 Differential
Continuous TIA
Booth # 1420
High-Speed
Serial Interface Test
in Production
Assure Device Interoperability In
Real-World Environments
2004