Paper by F.L. Kastensmidt, G. Neuberger, L. Carro, R. Reis
Talk by Nick Boyd
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Exploring techniques for detecting and
dealing with radiation-induced faults in
FPGAs
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Why?
 Drive to use commercial off-the-shelf to minimize
cost and development time (for space apps)
 As technology gets smaller, radiation becomes an
issue even at ground level
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Incident radiation deposits energy
 creation of electron-hole pairs and secondary ionizations produce
transient current pulse
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Can change a ‘0’ to a ‘1’ or vice versa, often called “bit flip”
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In combinational logic: Single Event Transient (SET)
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In sequential (or memory): Single Event Upset (SEU)
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In FPGAs there are further considerations
 SEU in the configuration SRAM (logic, routing)
 SET in combinational FPGA fabric
 SEU in BlockRAM
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Effects of SEU in configuration fabric
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TMR = Triple Modular Redundancy
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Logic is triplicated and results are accepted by majority vote
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Everything is tripled; including combinational, sequential, routing
and i/o
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Benefits
 Able to detect and correct SEU\SET anywhere in
the FPGA
 No performance penalty
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Drawbacks
 Very large area/resource penalty
(particularly problematic for i/o pads)
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A new technique proposed by the authors of
this paper
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DMR-CED: Double Modular Redundancy with
Concurrent Error Detection
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Motivation: Want to find a way that is as
reliable as TMR in detecting/correcting errors
with less area overhead
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CED = Concurrent Error Detection
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Exploits some property of the logic block to
find error
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Time-redundant examples:
 bit-wise inversion
 re-computing with shifted operands (RESO)
 re-computing with swapped operands (REWSO)
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Result calculated from direct input and stored
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Input then encoded, new result calculated
and decoded
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Two outputs
compared –
should be equal
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How can we use CED?
 Only duplicate combinational logic
 Use CED to determine the faulty module only if
there is disagreement
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Three sample sequential circuits tested
 8-bit multiplier
 8-bit ALU
 FIR filter
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Sample circuits generated then each node was
replaced with a multiplexor which either passes
‘correct’, ‘0’, or ‘1’
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Able to simulate every possible SEU fault
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Benefits
 Reduces area required for combinational logic (by
a significant amount in some cases)
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Drawbacks
 Significantly more complicated due to CED
 CED circuit needs to be chosen to be optimized
for each combinational circuit you protect
 Speed reduced by as much as 50%
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Reasonably well written and complete
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Necessary to read the references to
understand the minutiae of underlying
principles
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DMR-CED probably only useful under very
specific conditions
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