Partial Reconfigurable
Designs
Multi-layer Floorplanning
Max Walton
Outline
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Introduction
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Floorplanning
Model
Proposed Floorplanner
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Challenges
Data Representation
Cost Functions
Moves
Matching
Results
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Introduction
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Partial Reconfiguration
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Difference-based (used in this paper)
Module-based
Issues
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Reconfiguration overhead
Time issues
Placement
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Floorplanning Terminology
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Static Module
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AKA: fixed module
A module that will not be reconfigured
Non-static module
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AKA: reconfigured modules
Modules that will be reconfigured between
designs
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Introduction: Challenges
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Reuse Matching
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Reuse Placement
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Which components overlap during configuration?
Where do the components need to be placed?
Reuse Interface
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How are such components connected to
reconfigurable regions?
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Floorplanning
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Placing components on a chip
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Differs from placement by only placing large
sized components on chip
Does not look at logic
Complements Placement
Outputs coordinates defining positions of
block on device
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Floorplanning
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Three types of floorplanning
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Independent
Dependent
Combined
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Floorplanning
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Simulated Annealing Based
Fixed Outline Floorplanning
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Constrain design in rectangular shapes of fixed
aspect ratio
Parquet
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Area
Wirelength
Aspect Ratio
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Model
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Frames
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Span n columns
Module spans contiguous set of frames (hor/vert)
Time to reconfigure linear function of number
of frames to be reconfigured
Minimize number of frames by placing fixed
and reconfigurable parts in separate frames
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Assumptions
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Complete Sequence of Designs is known
No Data Dependency Between Designs /
Input and Output Buffered in Static region
Soft blocks
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Block can be placed anywhere on device
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Changing of aspect ratio is allowed
Heterogeneous floorplanning out of scope
All designs are timing critical
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Reusable Components
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Keep interconnects outside of static regions
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Use of whitespace for interfaces
Maximize A1,2 and Areused
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Proposed Floorplanner (FFPR)
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Built from Parquet floorplanner
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Routing congestion
Total Frames
Handles multiple designs simultaneously
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Definition
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Given design D1 with a set of modules M1 = {m1, …,
mn1} and corresponding connectivity,
Given design D2 with a set of modules M2 = {m1, …,
mn2} and corresponding connectivity,
Given a set of common modules between the two
designs M12,
Floorplan each design such that the total area and
wirelength in each design is minimized as well as
total reconfiguration area is minimized.
Extensible to k>2 reconfigurable designs
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FFPR
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FFPR: Data Representation
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Placement by Sequence Pairs
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Exact placement found with horizontal and
vertical graphs
Algorithm runs in O(n2)
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FFPR: Data Representation
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Two-layer Sequence pair
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Non-static have no left-right or up-down
relationship between each other
Horizontal and vertical graphs are connected
through static nodes only
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FFPR: Data Representation
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FFPR: Cost Functions
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Scaling factors
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Sum to 1
Represent respective weights of area, aspect ratio, frames,
wirelength, congestion
Area
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Minimum bounding box encompassing all designs
Negative if new area is less than current
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FFPR: Cost Functions
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Aspect Ratio
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Computed as a penalty function
Computes change in cost of the aspect ratio
Wirelength
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Adds wirelength of each interconnect in design
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Half-perimeter bounding box is used for each interconnect
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FFPR: Cost Functions
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Congestion Cost
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Probability Congestion model
2D array of bins (CLBs in Virtex 4)
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A pin lies in only one bin
A bin may contain multiple pins
Sum of probabilites of all the paths that pass through bin
Bin is congested if its congestion exceeds a threshold
Calculated as sum of excess congestion of each bin
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FFPR: Cost Functions
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Reconfiguration Frames Cost
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Computed by looking at the fixed and
reconfigurable regions compared with next design
Consecutive design frames are added together to
get total number
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FFPR: Moves
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Moves on Blocks
1)
2)
3)
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Changing orientation of a block
Changing aspect ratio
Changing whitespace along the border
Moves on Data Representation
1)
2)
3)
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Compaction: swapping random modules
Compaction: moving block left/right or up/down
Matching
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Moves: Changing the Whitespace
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Add four offsets to the blocks
n, e, w, s
 Range {0 .. 5}
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FFPR: Matching
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2 designs is equivalent to bipartite matching
Matching for multiple designs
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Leads to many cases
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FFPR: Matching
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Results
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Matching:
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50% savings on frames (50% partial matching)
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Results
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Direction of matching can impact design
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Dependent Mode as much as 3X wirelength of
combined/independent
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D1  D2 vs. D2  D1
50% higher on average
Combined 9% more wirelength than independent
Multilayer vs. traditional floorplanner
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12% better clock period on average
Reduces place and route time
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References
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“Multi-layer floorplanning for reconfigurable
designs”, L. Singhal and E. Bozorgzadeh, IET
Comput. Digit. Tech., 2007, 1, pp. 276-294
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Project
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Create a Scatter Search implementation in
Celoxica Handel-C
Search out better performance from Handel-C
version of SS
Use Handel-C constructs to gain better
performance
Attempt multiple approaches of
implementation (time permits)
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Project Status
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Used C code for 0-1 Knapsack Problem from
“Scatter Search: Methodology and
Implementations in C” by Laguna and Marti
Currently converting to avoid pointer use and
use less complex data structures more
inherent in hardware
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