Testimise projekteerimine:
Labor 2
BIST Optimization
Sergei Kostin
BIST (Built-in Self Test)
ehk sisseehitatud isetestimine on digitaalskeemi
(mikroskeemi, plaadi, süsteemi jms) omadus iseennast
testida.
Typical BIST Architecture
Test Pattern
Generator
(PRPG)
BIST
Control
Unit
Circuit Under
Test (CUT)
BIST
Memory
........
........
Output Response
Analyzer (MISR)
2
Built-In Self-Test
 Motivations for BIST:







Need for a cost-efficient testing (general motivation)
Doubts about the stuck-at fault model
Increasing difficulties with TPG (Test Pattern Generation)
Growing volume of test pattern data
Cost of ATE (Automatic Test Equipment)
Test application time
Gap between tester and UUT (Unit Under Test) speeds
 Drawbacks of BIST:




Additional pins and silicon area needed
Decreased reliability due to increased silicon area
Performance impact due to additional circuitry
Additional design time and cost
3
BIST Benefits
 Faults tested:
 Single stuck-at faults
 Delay faults
 Single stuck-at faults in BIST hardware
 BIST benefits







Reduced testing and maintenance cost
Lower test generation cost
Reduced storage / maintenance of test patterns
Simpler and less expensive ATE
Can test many units in parallel
Shorter test application times
Can test at functional system speed
4
Economics – BIST Costs
 Chip area overhead for:
•
•
•
•
Test controller
Hardware pattern generator
Hardware response compacter
Testing of BIST hardware
 Pin overhead -- At least 1 pin needed to activate BIST




operation
Performance overhead – extra path delays due to
BIST
Yield loss – due to increased chip area or more chips
In system because of BIST
Reliability reduction – due to increased area
Increased BIST hardware complexity – happens
when BIST hardware is made testable
5
BIST: Exhaustive test
Universal test sets
1. Exhaustive test (trivial test)
2. Pseudo-exhaustive test
Properties of exhaustive tests
1. Advantages (concerning the stuck at fault model):
- test pattern generation is not needed
- fault simulation is not needed
- no need for a fault model
- redundancy problem is eliminated
- single and multiple stuck-at fault coverage is 100%
- easily generated on-line by hardware
2. Shortcomings:
- long test length (2n patterns are needed, n - is the number of inputs)
- CMOS stuck-open fault problem
6
Problems with BIST: Hard to Test Faults
The main motivations of
using random patterns
are:
Problem: Low fault coverage
- low test generation cost
Patterns from LFSR:
- high initial efficiency
1
Pseudo-random
test window:
2n-1
Fault Coverage
Hard
to test
faults
Dream solution: Find LFSR such that:
2n-1
1
Hard
to test
faults
Time
7
Problems with Pseudo-Random Test
The main motivations
of using random
patterns are:
Problem: low fault coverage
- low generation cost
- high initial efeciency
&
1
Fault Coverage
LFSR
Decoder
Counter
Reset
If Reset = 1 signal has probability 0,5 then
counter will not work and
1 for AND gate may never be produced
Time
8
Pseudo-Random Test Generation by LFSR
Problems:
 Very long test
application time
 Low fault coverage
 Area overhead
 Additional delay
Time
Fault Coverage
Fault Coverage
breakpoint
Possible solutions
Weighted pattern PRPG
Combining pseudo-random
test with deterministic test
 Hybrid BIST
 Multiple seed (Reseeding)
Time
9
Hybrid Built-In Self-Test
Deterministic patterns
ROM
Pseudo-random
SoC
patterns
...
...
Core
PRPG
...
.
.
.
BIST Controller
...
CORE UNDER
TEST
MISR
Pseudo-random Test
Hybrid test set contains
pseudo-random and
deterministic vectors
Pseudo-random test is
improved by a stored test
set which is specially
generated to target the
random resistant faults
Optimization problem:
Where should be this
breakpoint?
Determ. Test
10
Hybrid BIST Technique
PR (pseudo-random patterns)
ATP (deterministic patterns)
seed / poly
100%
100%
100%
11
BIST Optimization Challenges
ATPG
curve
Fault Coverage (%)
ATPG patterns
from memory
slow growth
section
fast growth
section
PRPG
curve
Time (clk)
12
Reseeding (Multiple Seeds)
The main motivations
of using random
patterns are:
Problem: low fault coverage  long PR test
- low generation cost
- high initial efeciency
Pseudo-random test:
2n-1
1
Fault Coverage
Hard
to test
faults
Solution:
many seeds
1
Pseudo-random test:
2n-1
Time
13
Reseeding Optimization Problem
Using many seeds:
Pseudo-random test:
Seed 1
2n-1
1
L
Problems:
How to calculate the number
and size of blocks?
Seed 2
Deterministic
test (seeds):
Which deterministic patterns
should be the seeds for the
blocks?
Block
size:
100% FC
M
Seed 1
Seed 2
Seed n
Pseudorandom
sequences:
Constraints
Seed n
Minimize L at given M and 100% FC
14
Cost Calculation for Hybrid BIST
CTOTAL =  T +  M(k)
# faults
not
detected
PR test
length
Cost
Number of remaining
faults after applying k
pseudorandom test
patterns rNOT(k)
Total Cost
CTOTAL
T
Cost of
pseudorandom
test patterns CGEN
Cost of stored
test CMEM
 M(k)
min CTOTAL
Number of pseudorandom test
patterns applied, k
Pseudorandom Test
Det. Test
k
rDET(k)
1
2
3
4
5
10
20
50
100
200
411
954
1560
2153
3449
4519
4520
155
76
65
90
44
104
44
51
16
18
31
18
8
11
2
2
1
rNOT(k
839
763
698
608
564
421
311
218
145
114
70
28
16
5
3
1
0
# tests
needed
FC(k)
15.6%
23.2%
29.8%
38.8%
43.3%
57.6%
68.7%
78.1%
85.4%
88.5%
93.0%
97.2%
98.4%
99.5%
99.7%
99.9%
100.%
t(k)
104
104
100
101
99
95
87
74
52
41
26
12
7
3
2
1
0
15
Variant 5
16
ISCAS’ 85 benchmark circuit
17
Task 1: Pseudo-random test generation
 Find out the maximum fault coverage for given circuits
applying tuned ATPG.
 Algorithms  New = ATPG
ATPG (Automated Test Pattern Generator)
• Genetic
• Deterministic
• Random
ATPG algorithms description:
• Turbo Tester v02.10.pdf (edu.pld.ttu.ee 
minu materjalid)
• 4.2 Test Pattern Generation
18
Task 1: Pseudo-random test generation
 Choose “good” seed and polynomial to generate
effective pseudo-random test.
• “good” polynomial: random or primitive
• “good” seed: pattern testing HTTF (hard-to-test faults)
(select from ATPG test)
19
Task 1: Pseudo-random test generation
 Pseudo-random test sequence must have
• maximum fault coverage (same as for ATPG)
• length of test must be in the range T<= length<=1,2T
where T – Time Constraint from Table 2.
 Example: c1908  T = 7500 and 1,2T = 1,2*7500 =
9000  7500 <= test length <= 9000
 Hint: When generating a test put the number of clock
cycles equal to 1,2T
• if maximum fault coverage achieved within given test then cut out
last patterns that do not give additional fault coverage
 Use Type I and Type II generators.
 Fill in the table
20
Task 2 and 3
 Reseeding algorithm:
 Find complete test (max. fault coverage) for given circuit, using the
best PRPG (Type I LFSR) test sequence achieved in task 1.
 Perform experiments stepping through the constraint values and
choose 5 results (test must comply with the constraints specified in
your variant). Example: c1908 M = 1, 2, 3…10 (min.step = 1); T
= 7500, 7000, 6500… (min.step = at least 5% of T).
 Hybrid BIST algorithm:
 Find complete test (max. fault coverage) for given circuit, using the
best PRPG (Type I LFSR) test sequence achieved in task 1.
 Perform experiments and choose 5 evenly distributed results (test
must comply with the constraints specified in your variant).
21
Reseeding and Hybrid Algorithms
 PRPG
• Load  use saved sequence of
pseudo-random test patterns
• Sync  use generated in PRPG
panel sequence of test patterns
 Constraint
• Time  test length (number of pseudo-random test patterns)
• Memory (vectors)  number of deterministic test patterns
stored in memory
22
Reseeding and Hybrid Algorithms
 Load model (AGM panel)
 Load or Sync PR test (PRPG
panel)
 Generate ATPG test (press
New or Load button)
 Select Time or Memory(vectors )
Constraint and enter the constraint
 Run
In order to Run Reseeding or Hybrid Algorithm with
another constraint: just change constraint and press Run
23
Reseeding: calculating BIST cost
Test Length (T) = 3770, FV = 99,48%
Block size = 377  M = 3770/377 – 1 = 9
Cost = 3770 + 400*9 = 7370
24
Hybrid: calculating BIST cost
M = 10, FV = 99,48%
Test Length (T) = 2887 + 10 = 2897,
Cost = 2897 + 400*10 = 6897
25
Fill in the Result Table
Circuit 1: C1908
Reseeding
Hybrid BIST
Calculated Test
Memory Fault
Calculated Test
Memory Fault
Cost:
Length Vectors
Coverage Cost
Length Vectors
Coverage
7370
3770
9
99,48
6897
2897
10
99,48
7850
4250
9
99,48
6100
4500
4
99,48
Memory Constraint: min. step is 1
• Example: c1908 constraint = 15  M = 1,2,3,...,15
Time Constraint: min. step is at least 5% of constraint and number of
memory vectors must change
• Example: c1908 constraint = 7500  T = 7500, 7000, 6500...
• NB! if cannot find 5 satisfactory tests for Reseeding, decrease
min. step or use Memory constraint instead
NB! Try to use the same constraints for both algorithms  this helps
to compare effectiveness of Reseeding and Hybrid algorithms
26
Task 4
 Results evaluation:
 According to the marginal results obtained in
task 2 and 3 construct the Cost curves on the
same graph for Reseeding and Hybrid BIST
algorithms.
 Compare results of Reseeding and Hybrid
algorithms.
27
BIST Cost Curves for Circuit c1908
10000
9000
8000
Cost
7000
6000
5000
Reseeding
Hybrid
4000
3000
2000
1000
0
8
10
12
14
15
Memory (vectors)
28