ASM and Register Transfer Level
Overview
°  System design must be modular
•  Easier to represent designs with system-level blocks
°  Register transfer level represents transfers between
clocked system registers
•  Shifts, arithmetic, logic, etc.
°  Algorithmic state machine
•  Alternate approach to representing state machines
°  Status signals from datapath used for control path
°  Algorithmic state machine chart shows flow of
computation
System-level Design
°  Difficult to represent a design with just one state
machine
°  A series of control and data paths used to build
computer systems
°  Helps simplify design and allow for design changes
Main
Memory
Processor
Disk
Keyboard
Registers and Data Operations
°  Activity and performance in computers defined on
register-to-register paths
°  Digital system at register transfer level specified by
three components
• 
• 
• 
The set of registers in the system
Operations to be performed on registers
Control that is applied to registers and sequence of operations
Function
Representation of Register Transfer Flow
°  Arrow indicates transfer from one register to another
• 
R2 ← R1
°  Conditional statements can help in selection
• 
If (T1 = 1) then R2 ← R1
°  Clock signal is not generally included in register
transfer level statement
• 
Sequential behavior is implied
°  Multiple choices also possible
• 
If (T1 = 1) then (R2 ← R1, R2 ← R2)
How could these statements be implemented in hardware?
Other representative RTL operations
°  Addition
• 
R1 ← R1 + R2
°  Increment
• 
R3 ← R3 + 1
°  Shift right
• 
R4 ← R4
°  Clear
• 
R5 ← 0
°  Transfer doesn't change value of data begin moved
How could these statements be implemented in hardware?
Algorithmic State Machines (ASM)
° 
Flowchart specifies a sequence of procedural steps and
decision steps for a state machine
° 
Translates word description into a series of operations with
conditions for execution
° 
Allows for detailed description of control and datapath
Algorithmic State Machines – State Box
°  ASM describes operation of a
sequential circuit
°  ASM contains three basic
elements
• 
• 
State box
Decision box
• 
Condition box
°  State box indicates an FSM
state
• 
Box also indicates operation to be
performed
°  Binary code and state name
also included
Decision Box
°  Describes the impact of input on control system
°  Contains two exit paths which indicate result of
condition
°  More complicated conditions possible
°  Implemented in hardware with a magnitude
comparator
Conditional Box
°  Indicates assignments following a decision box
°  Generally indicates data transfer
ASM Block
°  Paths exist between state boxes
°  Each state box equivalent to one state
ASM Block
°  Equivalent to State Diagram
Concept of the State Machine
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Res et
0
Even
[0]
1
0
1
Odd
[1]
State
Diagram
Present State
Even
Even
Odd
Odd
Input
0
1
0
1
Next Stat e
Even
Odd
Odd
Even
Symbolic State Transition Table
Present S tate
0
0
1
1
Input
0
1
0
1
Ne xt St ate Out put
0
0
1
0
1
1
0
1
Encoded State Transition Table
°  Note: Present state and output are the same value
°  Moore machine
Out put
0
0
1
1
ASM for Odd Parity Checker
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Res et
Even
0
Even
[0]
1
0
0
Out ← 0
1
0
Odd
[1]
In = 1
1
State
Diagram
Odd
1
Out ← 1
0
In = 1
1
Algorithmic State Machines (ASMs)
State_Name
Moore outputs
(a)
0
Input
(b)
Figure 8.42
1
Mealy
outputs
(c)
ASM Representation of a Mealy Machine
z=0
A
0
1
X
0/0
A
1/0
0/1
X/Y
z=0
1/1
0/0
B
1/0
C
B
1
X
(b)
z=1
0
z=0
z=0
C
0
X
z=1
1
(a)
Figure 8.43
ASM Representation of a Moore Machine
A
z=0
0
1
X
0
B
z=1
0
X
A/0
1
1
1
1
B/1
0
0
C/0
(b)
C
z=0
0
X
Figure 8.44
1
(a)
Eight-Bit Two’s Complementer ASM -Example 8.19
A
Look for
first 1 bit
z=0
0
x
1
z=1
B
Complement
remaining bits
z=1
0
x
z=0
1
Figure 8.45
Design Example: Binary Multiplier
°  Two basic approaches
– implementing the control unit
•  Hardwired control
-  less costly
-  faster operation speeds
•  Microprogrammed control
-  many complex instructions
Design Example: Binary Multiplier (2)
°  Binary Multiplier
•  Multiplication of two unsigned binary numbers
•  Hand multiplication example
Need n binary a
dditions
shift
FIGURE 8-4
Hand Multiplication
Example
Design Example: Binary Multiplier (3)
•  Hardware multiplication example
Design Example: Binary Multiplier (4)
°  Multiplier Datapath
n operations occur,
n-1 down through 0
external contr
ol input
10011
4
Stores the Cout,
Reset to 0 during
the right shift
FIGURE 8-6 Block Diagram for Binary Multiplier
S0
IDLE
0
Start=1
Register A
S1
COUNTER P
1
CLEAR R,
LOAD A,B,P
Register B
Cout
S2
ADDER
1
C
Register R
Register R
Left-half
Right-half
B(0)=1
0
P=0
0
S3
SHR B,R, C
DEC P
1
RLßRL+A
S0
P.S
Start=1
N.S
Output
S0(00)
Start=0
S0(00)
S0(00)
Start=1
S1(01)
S1(01)
Dn’t Care
S2(10)
Clear R, Load A,B,P
S2(10)
B(0)=1
S3(11)
Load RL
S2(10)
B(0)=0
S3(11)
S3(11)
Not(P=0)
S2(10)
SHR B,R,C, DEC P
S3(11)
P=0
S0(00)
SHR B,R,C, DEC P
IDLE
0
Start=1
S1
1
CLEAR R,
LOAD A,B,P
S2
1
0
3
Load RL
CLEAR R, LOAD A,B,P
2
SHR B,R, C
DEC P
Clock
1
B(0)=1
FF
D1
DECODER
FF
D0
B(0)=1
0
P=0
0
S3
SHR B,R, C
DEC P
1
RLßRL+
P.S(D1D0)
Start=1
N.S
Output
S0(00)
Start=0
S0(00)
S0(00)
Start=1
S1(01)
S1(01)
Dn’t Care
S2(10)
Clear R, Load A,B,P
S2(10)
B(0)=1
S3(11)
Load RL
S2(10)
B(0)=0
S3(11)
S3(11)
Not(P=0)
S2(10)
SHR B,R,C, DEC P
S3(11)
P=0
S0(00)
SHR B,R,C, DEC P
P(3) P(2) P(1) P(0)
Q1/Q0
0
1
Q1/Q0
0
1
0
Start
0
0
0
1
1
1
0
1
1
Not(P=0)
D0=Q1’Q0’.Start+Q1.Q0’
(P=0)=P(0)’.P(1)’.P(2)’.P(3)’
=(P(0)+P(1)+P(2)+P(3))’
(P=0)’=P(0)+P(1)+P(2)+P(3)
D1=Q1’.Q0+Q1.Q0’+Q1.Q0’.Not(P=0)
0
Register R
Left-half
Right-half
REGISTER R
CLEAR R, LOAD A,B,P
Register R
3
SHR B,R, C
DEC P
C
COUNTER P
Register B
2
B(0)=1
DECODER
Register A
1