Core to Memory Interconnection
Implications for Forthcoming
On-Chip Multiprocessors
1
Carmelo Acosta Francisco J. Cazorla
1,2
1,2
Alex Ramírez
Mateo Valero
1
UPC-Barcelona
2
Barcelona Supercomputing Center
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Overview

Introduction

Simulation Methodology

Results

Conclusions
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Introduction


As Process Technology advances it is more
important what to do with transistors.
Current trend to replicate cores.




Intel: Pentium4, Core Duo, Core 2 Duo, Core 2 Quad
AMD: Opteron Dual-Core, Opteron Quad-Core
IBM: POWER4, POWER5
Sun Microsystems: Niagara T1, Niagara T2
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Introduction
Power4 (CMP)

Power5 (CMP+SMT)
Memory Subsystem (green) spreads over more
than half the chip area.
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Introduction

Each L1 is connected to each L2 bank with a busbased interconnection network.
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Goal

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Is directly applicable prior research in the
SMT field in the new CMP+SMT scenario?
NO…we have to revisit well-known SMT
ideas.
 Instruction Fetch Policy
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ICOUNT
Fetch
ROB
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ICOUNT
Fetch
ROB
FETCH
Stalled
L2 miss


Processor’s resources balanced between running
threads.
All resources devoted to blue thread unused until
L2 miss resolution.
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FLUSH
Fetch
ROB
FLUSH
Triggered
L2 miss

All resources devoted to the pending instructions
of the blue thread are freed.
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FLUSH
Fetch
Thread
Stalled
ROB
L2 miss


Freed resources allow additional forward progress.
L2 miss late detection  L2 miss prediction.
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Single vs Multi Core
L2 b0
L2 b1
L2 b2
L2 b3
More pressure on both:
• Interconnection Network
• Shared L2 banks
I$ D$
Core
L2 b0
L2 b1
L2 b2
L2 b3
I$ D$
I$ D$
I$ D$
I$ D$
Core
Core
Core
Core
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Single vs Multi Core
L2 b0
L2 b1
L2 b2
I$ D$
L2 b3
More Unpredictable L2 Access Latency
- BAD for FLUSH
Core
L2 b0
L2 b1
L2 b2
L2 b3
I$ D$
I$ D$
I$ D$
I$ D$
Core
Core
Core
Core
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Overview

Introduction

Simulation Methodology

Results

Conclusions
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Simulation Methodology

Trace driven SMT simulator derived from SMTsim.

C2T2, C3T2, C4T2 multicore configurations.
(CXTY, where X= Num. Cores and Y= Num. Threads/Core)
L2 b0
L2 b1
L2 b2
L2 b3
I$ D$
I$ D$
I$ D$
I$ D$
Core
Core
Core
Core
Core Details
(* per thread)
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Simulation Methodology

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Instruction Fetch Policies:

ICOUNT

FLUSH
Workload classified per type:



ILP  All threads have good memory behavior.
MEM  All threads have bad memory behavior.
MIX  Mixes both types of threads.
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Overview

Introduction

Simulation Methodology

Results

Conclusions
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Results : Single-Core (2 threads)

FLUSH yields 22% average speedup over ICOUNT,
in MIX workloads.

Mainly on MEM/MIX workloads
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Results : Multi-Core (2 threads/core)
+Cores  -Speedup

FLUSH drops to 9% average slowdown over
ICOUNT in a four-cored multicore.
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Results : L2 Hits Latency on Multi-Core
+Cores  +latency
+dispersion
L2 hit latency (cycles)
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Results : L2 miss prediction

In this four-cored example, the best choice is
predicting L2 miss after 90 cycles.
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Results : L2 miss prediction

But, in this other four-cored example the best
choice is not to predict L2 miss.
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Overview

Introduction

Simulation Methodology

Results

Conclusions
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Conclusions


Future high-degree CMPs open new challenging research
topics in CMP+SMT cooperation.
The CMP outer cache level and interconnection
characteristics may heavily affect SMT intra-core
performance.


For example, FLUSH relies on a predictable L2 hit latency,
heavily affected in a CMP+SMT scenario.
FLUSH drops from 22% average speedup to 9% average
slowdown when moving from single-core to quad-core
configuration.
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Thank you
Questions?
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Feb. 11th 2007