Reducing the Storage Requirements of a Test Sequence
by Using a Background Vector
Irith Pomeranz1
School of Electrical & Computer Eng.
Purdue University
W. Lafayette, IN 47907, U.S.A.
Abstract - We describe a storage scheme for functional
test sequences where a test sequence T is associated
with a primary input vector B called a background
vector. T is stored by storing only the differences
between its test vectors and B . We describe a procedure for computing a background vector B for a
given test sequence T . We also describe a procedure
that modifies T so as to reduce its storage requirements with respect to B . We present experimental
results demonstrating that the single background vector B , computed based on T , allows T to be modified
such that a vast majority of its entries are equal to the
corresponding entries of B . Consequently, storage of T
reduces to storage of a small number of entries.
I. INTRODUCTION
Structural tests are applied to a sequential circuit
through scan chains. Functional tests avoid the use of
scan chains, and are applied under the functional mode of
operation of the circuit. A functional test sequence
specifies the values to be applied to the primary inputs of
the sequential circuit during test application. Functional
test sequences may be used for manufacturing testing
since they detect defects that are not detected by scanbased tests [1], or to avoid overtesting [2]-[3]. They may
also be used for speed binning and for simulation-based
design verification.
Most test generation procedures for synchronous
sequential circuits [4]-[8] construct a test sequence T by
concatenating test subsequences. Test subsequences may
be generated by a deterministic [4] or a simulation-based
[5]-[8] process. These processes introduce new input vectors into T as a result of a branch-and-bound process [4]
or through operators such as single-bit changes or mutation [5]-[8]. These procedures do not consider the storage
requirements of the resulting test sequence. Storage
requirements are important since the length of a functional
test sequence can be high, and under some test strategies,
the sequence may have to be stored in an on-chip memory
for at-speed application [9]-[12].
1. Research supported in part by SRC Grant No. 2007-TJ-1643.
2. Research supported in part by SRC Grant No. 2007-TJ-1642.
978-3-9810801-6-2/DATE10 © 2010 EDAA
Sudhakar M. Reddy2
Electrical & Computer Eng. Dept.
University of Iowa
Iowa City, IA 52242, U.S.A.
Extensive research has been done on reducing test
data volume and test application time for scan circuits
[13]-[27]. Test application time is reduced by using test
compaction [14]-[17] and multiple scan chains [18], [19],
[24]. Encoding methods such as those in [21]-[23] and
[25]-[26] reduce the test data volume by encoding test
vectors. Encoding methods can be applied to functional
test sequences as well. The method described in this work
modifies a functional test sequence in order to reduce its
storage requirements. After the sequence is modified as
proposed here, the methods of [21]-[23] and [25]-[26] can
be used to achieve additional reductions in test data
volume. An earlier work that modified test vectors for
full-scan circuits targeted the reduction of test data
volume when statistical encoding is used [20].
Storage requirements of functional test sequences
were also considered in [28]. The goal of one of the procedures described in [28] is to reduce the number of different primary input vectors included in a test sequence.
This procedure relies on a storage scheme where each distinct primary input vector is stored only once. A sequence
of indices into the set of distinct vectors is used for storing
the test sequence. A similar procedure is used for reducing the number of distinct fault free output vectors. The
results presented in [28] indicate that this scheme is effective for storage of output vectors. On the input side, the
number of distinct test vectors remains relatively high
even after optimization.
In this work we propose a storage scheme for functional test sequences that focuses on storage of the primary input sequence. On the output side we assume that
output compression or the approach of [28] will be used.
Under the proposed scheme, a test sequence T is associated with a primary input vector B called a background
vector. The test sequence T is stored by storing only the
differences between its test vectors and B . For example,
with a background vector B = 0000, the test sequence T =
0000 0001 0000 0000 0101 0000 assigns the same value
as B to all but three entries corresponding to the three 1s
in T . Only the indices of these three entries need to be
stored. To support the proposed scheme we describe a
procedure for computing a background vector B for a
given test sequence T . We also describe a procedure that
modifies T so as to reduce its storage requirements with
respect to B . Modification of T consists of three steps.
The first step extends T in order to allow more flexibility
in changing its entries such that they would be equal to the
corresponding entries of B . The second step changes
entries of T that are different from the corresponding
entries of B . The third step consists of static test compaction to remove unnecessary test vectors from T . The
effectiveness of this approach is based on the following
experimental observations.
(1) It is possible to compute an effective background vector B based on T by using a simple and efficient method.
(2) It is then possible to modify T such that most of its
entries would be equal to the corresponding entries of B .
We note that obtaining new test vectors for fullscan circuits by changing certain bits of existing test vectors was considered in [29]-[32] for built-in self-test.
These procedures can be viewed as using several different
background vectors that are modified to obtain new test
vectors. Our goal in this work is to use a single background vector, and we consider functional test sequences.
Certain encoding techniques [33] are also based on
changes with respect to a single background vector (typically the all-0 vector). However, in these cases the background vector is fixed in advance. We allow the background vector to be selected and the test data to be
modified such that the resulting storage requirements
would be as small as possible.
The paper is organized as follows. In Section II we
discuss the storage of a test sequence T based on a background vector B . In Section III we describe the computation of B for a given test sequence T . In Section IV we
describe a procedure for modifying T based on the background vector B selected for it. In Section V we present
experimental results.
II. STORAGE OF A TEST SEQUENCE T
In this section we discuss the storage of a test
sequence T using a background vector B . We use the following notation. The number of primary inputs of the circuit is denoted by n . The value of primary input i under
B is denoted by B (i ) for 0 ≤ i < n . Thus, B = B (0) B (1)
. . . B (n −1). The length of T is denoted by L . The test
vector at time unit u of T is denoted by T (u ) for
0 ≤ u < L . The value of primary input i at time unit u of
T is denoted by T (u ,i ) for 0 ≤ i < n and 0 ≤ u < L .
With a background vector B , a test sequence T is
stored as a list DIFF (T ,B ) of entries (u ,i ) such that
T (u ,i ) ≠ B (i ). For example, with a background vector
B = 0000, the test sequence T = 0000 0001 0000 0000
0101 0000 is stored as DIFF (T ,B ) = {(1,3),(4,1),(4,3)}
corresponding to the 1s of T .
For a circuit with n primary inputs and a test
sequence T of length L , we compute the storage requirements of T in two ways.
(1) Conventional storage of T requires a number of bits
equal to CONV_STOR = nL .
(2) Storage based on B requires storage of DIFF (T ,B ).
An entry of DIFF (T ,B ) is a pair (u ,i ), which is an index
into T . The number of bits to represent such an index is
log2(nL ). The total number of bits for this storage
scheme is BACK_STOR = | DIFF (T ,B ) | log2(nL ).
We associate with T the storage requirements
STOR = min{CONV_STOR ,BACK_STOR }. Experimental results presented later show that for a test sequence T
generated by sequential test generation, the conventional
storage scheme is preferable. Under the proposed procedure, we modify T into a test sequence Tmod that is
amenable to storage based on a background vector B . Let
the length of Tmod be Lmod . We will compare the conventional storage requirements for T , CONV_STOR = nL ,
with the storage requirements of Tmod based on B ,
BACK_STORmod = | DIFF (Tmod ,B ) | log2(nLmod ). The
condition BACK_STORmod < CONV_STOR will be
satisfied when | DIFF (Tmod ,B ) | < nL /log2(nLmod ).
III. COMPUTING A BACKGROUND VECTOR B
In this section we describe a procedure for selecting
a background vector B for a given test sequence T . Our
goal in selecting B is to ensure that the set DIFF (T ,B )
would be as small as possible.
For every primary input i , where 0 ≤ i < n , we find
the number of time units u such that T (u ,i ) = 0. We also
find the number of time units u such that T (u ,i ) = 1. We
denote these numbers by n 0(i ) and n 1(i ), respectively. We
select B (i ) as follows. If n 0(i ) > n 1(i ), we set B (i ) = 0.
If n 0(i ) < n 1(i ), we set B (i ) = 1. If n 0(i ) = n 1(i ), we
assign a 0 or 1 value to B (i ) randomly.
For illustration we consider a test sequence of
length 10 for ISCAS-89 benchmark circuit s 27. The
sequence is shown under column given of Table I. The
circuit has four primary inputs. We obtain B = 0001 as
follows. Based on n 0(0) = 5 and n 1(0) = 5 we assign a
value to B (0) randomly. We obtain B (0) = 0. Based on
n 0(1) = 7 and n 1(1) = 3 we set B (1) = 0. Based on n 0(2) =
6 and n 1(2) = 4 we set B (2) = 0. Based on n 0(3) = 3 and
n 1(3) = 7 we set B (3) = 1.
The background vector B computed above will
result in the smallest set DIFF (T ,B ) for T . Different
background vectors may result in different storage
requirements for the modified test sequence Tmod obtained
from T . However, since parts of T may have to be
retained in order to maintain the fault coverage, we prefer
to use a background vector that is most suitable for T .
IV. MODIFYING A TEST SEQUENCE BASED ON B
In this section we describe a procedure that accepts
a test sequence T , the set F of faults detected by T , and a
background vector B . The procedure modifies T based on
TABLE I
TEST SEQUENCE FOR s 27
given ext compl
u
0 0111 0111 0011
1 1001 1001 1001
2 0111 0001 0001
3 1001 0011 0001
4 0100 0001 0001
5 1011 0001 0001
6 1001 0001 0001
7 0000 0111 0001
8 0000 0001 0001
9 1011 0001 0001
10 0001 0001
11 0001 0001
0111 0101
12 1001 0001
13 0111 0001
14 15 1001 0001
16 0100
0000
17 1011 1011
18 1001 1001
0000 0001
19 0000 0000
20 1011 0001
21 B while ensuring that T continues to detect all the faults
in F . The first step of the modification extends T in order
to provide more flexibility for changing its entries so that
they would match those of B . The goal of the second step
is to reduce the size of the set DIFF (T ,B ). For this, the
procedure attempts to complement as many entries T (u ,i )
as possible where T (u ,i ) ≠ B (i ). The third step compacts
the test sequence in order to remove test vectors that are
unnecessary due to the extension or the complementation
steps. We describe the second step first, followed by the
first and the third steps. The three steps are iterated as
described at the end of this section.
A. Complementation
A basic step of complementing entries of T
proceeds as follows. For a constant N , we select a subset
Ecurr = {(u ,i ):T (u ,i )≠B (i )} of size N . We modify T by
setting T (u ,i ) = B (i ) for every (u ,i ) ∈ Ecurr . We then
determine whether all the faults in F are still detected by
T . Certain faults in F do not require fault simulation. If
the lowest time unit that appears in Ecurr is u min, there is
no need to simulate a fault from F that is detected by T
before time unit u min. We perform fault simulation only
for the remaining faults in F . If any of the faults in F is
not detected, we stop the fault simulation process and
undo the modification by complementing all the entries in
Ecurr again. Otherwise, we accept the modification.
We observed that certain faults cause complementation steps to fail more often than others. Such faults
should be simulated earlier to allow the fault simulation
process to end as early as possible and thus reduce the
fault simulation effort. We implement this as follows. Initially, und (f ) = 0 for every f ∈ F . If a complementation
step fails because a fault f remains undetected, we increment und (f ) by one. Fault simulation following a complementation step is done by order of decreasing values of
und (f ). Every step that fails causes und (f ) to be incremented for one fault, speeding up the fault simulation process for the succeeding steps.
The overall complementation process for T
proceeds as follows. For constants N 1 and N 2, we consider N = N 1, N 1/2, . . . , N 2. By selecting a large value
for N 1, we start by attempting to change a large number of
entries of T simultaneously in order to reduce the number
of fault simulation passes. We reduce N gradually to
allow more refined modifications of T . We use N 2 = 1 for
the smallest possible modifications. We use each value of
N repeatedly until no additional modifications of T are
possible with this value.
For every value of N , we first define a set E that
includes every entry (u ,i ) such that T (u ,i ) ≠ B (i ). We
select subsets Ecurr ⊆ E of size N randomly. Every time
a subset Ecurr is selected, we remove its entries from E ,
and attempt to modify T based on Ecurr as described earlier. This continues until E contains fewer than N entries.
For a given value of N , E initially contains at most
nL entries where n is the number of primary inputs and L
is the length of T . It takes nL /N steps until E contains
fewer than N entries. This is also the number of fault
simulation passes for a given N . In practice, the initial
number of entries in E is smaller than nL , and it decreases
as N is decreased. Therefore, the number of fault simulation passes is lower than this worst-case estimate.
For illustration we consider the test sequence of s 27
shown in Table I under column ext . The sequence is
obtained from the test sequence shown under column
given as described in the next subsection. The sequence
detects all 32 single stuck-at faults of the circuit, f 0, f 1,
. . . , f . We selected B = 0001 for the test sequence
31
shown under column given of Table I, and we use the
same vector for this example. The sequence under column
ext is different from B in 21 entries. We use N 1 = 4 and
N 2 = 1. With N = 4, the first subset of entries selected is
Ecurr = {(17,0), (19,3), (21,2), (18,0)}. Modifying T and
performing fault simulation we find that f 0 is not
detected. We stop the fault simulation process and undo
the change. The second subset of entries selected is
Ecurr = {(13,0), (0,2), (16,1), (12,2)}. Modifying T and
performing fault simulation we find again that f 0 is not
detected. We stop the fault simulation process and undo
the modification. The third subset of entries selected with
N = 4 is Ecurr = {(0,1), (21,0), (15,0), (3,2)}. Modifying
T and performing fault simulation we find that all the
faults are detected. This change is accepted.
After five subsets of size four are considered, the
size of E reduces to one, and N is reduced to 2. After considering N = 2 and 1, we obtain the test sequence shown
in Table I under column compl . This test sequence has
eight entries where it is different from B = 0001.
B. Extension
A given test sequence T , especially if it is compacted, provides limited flexibility for complementing
entries without losing fault detections. To provide more
flexibility for complementation, we extend the given test
sequence T into a test sequence Text as follows.
We perform logic simulation of T to find the first
time unit, usync , where the fault free state is fullyspecified. Based on usycn we extract a synchronizing
sequence S = T (0)T (1) . . . T (usync −1) from T . This is
always possible for test sequences that detect all the
detectable faults of benchmark circuits. S is the first
subsequence included in Text . This allows the next subsequences of Text to detect target faults even if they do not
synchronize the circuit.
The next subsequence added to Text is denoted by
V . It consists of L primary input vectors based on B . L is
the length of T , and it is used as an estimate of the length
of a subsequence that is needed for detecting target faults.
Initially we set V (u ) = B for 0 ≤ u < L . For 0 ≤ u < L
and 0 ≤ i < n , we complement V (u ,i ) with a small constant probability p . V has a small contribution to the
storage requirements of Text through DIFF (Text ,B ), since
most of its entries are equal to the corresponding entries
of B . Faults detected by this subsequence will provide
more flexibility for complementing other entries of Text so
as to reduce the final storage requirements.
Finally, we include in Text the given test sequence T
in order to ensure that all the faults detected by T will be
detected by Text . Overall, we obtain Text = S .V .T .
In the example of s 27 with the test sequence T
shown under column given of Table I, we obtain S =
0111 1001. We use p = 0.1. With B = 0001, we obtain
V = 0001 0011 0001 0001 0001 0111 0001 0001 0001
0001. After adding T we obtain the test sequence Text
shown in Table I under column ext .
For ease of reference we denote the test sequence
obtained from Text through complementation by Tcompl .
C. Compaction
The extension step introduces unnecessary test vectors into Text . After the complementation step, some of
the test vectors in Tcompl are needed for detecting target
faults, but other vectors may be unnecessary. We apply a
static test compaction procedure based on the one from
[34] in order to remove unnecessary test vectors from
Tcompl without reducing its fault coverage. Since static
test compaction only removes test vectors, it will not
increase DIFF (Tcompl ,B ). We attempt to reduce
DIFF (Tcompl ,B ) as much as possible by applying the
static test compaction procedure from [34] as follows.
The static test compaction procedure from [34] first
omits all or most of the test vectors from the test
sequence. It then restores test vectors so as to restore the
detection of target faults. We apply the static test compaction procedure in two phases. In the first phase we initially omit every test vector Tcompl (u ) such that
Tcompl (u ) ≠ B . With this initialization, the static test compaction procedure restore test vectors such that
Tcompl (u ) ≠ B only as necessary for detecting target faults.
In the second phase we initially omit all the test vectors
from the test sequence. We repeat the procedure of each
phase until it cannot reduce the test length any further.
We denote the test sequence obtained after static
test compaction by Tstat .
D. Iterations
In the process described so far, we start from a
given test sequence T . We extend T into Text , complement entries of Text to obtain Tcompl , and then apply static
test compaction to Tcompl to obtain Tstat . This process can
now be repeated as follows.
0
I
Let Tstat
= T . For I ≥ 1, let Tstat
be the test
sequence obtained at the end of iteration I . In iteration
I
I −1
I ≥ 1, we define Text
= S .V .Tstat
. Here, S and V are computed based on T and B as described earlier. Starting
I
from Text
we apply the complementation step to obtain
I
I
Tcompl , and static test compaction to obtain Tstat
.
We increase I and perform additional iterations as
I
long as the storage requirements of Tstat
are smaller than
I −1
those of Tstat .
V. EXPERIMENTAL RESULTS
We selected background vectors and modified test
sequences for synchronizable ISCAS-89 benchmark circuits and ITC-99 benchmark circuits. For T we use test
sequences obtained by sequential test generation followed
by static test compaction. We consider circuits where
conventional storage of T requires 1000 bits or more. To
I
obtain an extended test sequence Text
we use p = 1/L ,
where L is the length of the given test sequence T . This
implies that approximately n entries of each subsequence
V are different from the corresponding entries of B . For
the numbers of entries selected at every complementation
step we use N 1 = 1024 and N 2 = 1.
We report on the following test sequences: the
0
given test sequence, T , also referred to as Tgiven
; the test
I
sequence Text obtained after extending T at every iteration
I
I ; the test sequence Tcompl
obtained after applying the
I
I
complementation step to Text
; and the sequence Tstat
obtained after static test compaction.
The results are reported in Tables II and III. There
are several rows for every circuit corresponding to the
various test sequences obtained through all the iterations
until the last one that reduces the storage requirements.
Each row contains the following information.
Under column I we show the iteration number.
I = 0 corresponds to the given test sequence T (also
TABLE II
RESULTS FOR ISCAS-89 BENCHMARKS
I
len
ratio
type
DIFF
rtime storage
circuit
0 given 105
s208
213
1.00 C
1155 s208
238
1.13 1 ext
211
s208
32
101.61 1 compl 211
1 stat
32
16.84 B
352 0.3048
105
s208
0
given
516
308
1.00
C
1548 s382
s382
1
ext
1033
314
1.46
s382
1
compl
1032
72
119.11
s382
1
stat
570
53
82.36
B
583
0.3766
0
given
108
855
1.00
C
2052 s420
s420
882
0.32 1 ext
217
s420
29
36.53 1 compl 217
1 stat
107
28
12.37 B
308 0.1501
s420
0 given 1006
586
1.00 C
3018 s526
s526
592
1.15 1 ext
2014
s526
121
237.41 1 compl 2010
1 stat
1874
120
205.64 B
1560 s526
2 ext
2882
s526
125
1.66 2 compl 2882
s526
118
49.60 2
stat
1928
118
159.94
B
1534
s526
0.5083
0 given 101
1503
1.00 C
3535 s641
1 ext
206
s641
1593
1.56 1 compl 206
s641
169
699.71 1
stat
90
169
42.64
B
2028
s641
0.5737
s820
0
given
491
3193
1.00
C
8838
1 ext
983
s820
3225
4.15 1 compl 983
s820
313
2083.98 297
146.77 B
3861 s820
1 stat
392
s820
327
3.99 2 ext
884
2 compl 884
s820
294
306.91 2 stat
383
293
80.15 B
3809 0.4310
s820
s1196
1407
1.00 C
3332 0 given 238
s1196
1432
3.83 1 ext
478
1 compl 478
s1196
736
3565.76 1
stat
207
736
32.59
C
2898 s1196
s1196
2
ext
447
764
3.72
s1196
2
compl
447
736
808.89
732
35.18 C
2856 0.8571
2 stat
204
s1196
s1423
0
given
1024
7545
1.00
C
17408
1 ext
2056
s1423
7626
2.53 s1423
309
1885.08 1 compl 2055
253
271.44 B
3542 s1423
1 stat
767
2 ext
1799
s1423
334
3.03 2 compl 1799
s1423
240
296.61 2
stat
881
239
121.65
B
3346 s1423
s1423
314
3.13 3 ext
1913
s1423
3
compl
1913
232
356.79
224
157.00 B
3136 0.1801
3 stat
825
s1423
0
given
455
1531
1.00
C
3640 s1488
s1488
1
ext
911
1543
6.14
s1488
256
1062.21 1 compl 911
256
76.19 B
3072 0.8440
1 stat
434
s1488
0 given 646
s5378
8790
1.00 C 22610 s5378
9048
1.08 1 ext
1306
s5378
513
991.63 1 compl 1305
513
39.98 B
7695 0.3403
1 stat
627
s5378
0 given 150
2351
1.00 C
5250 s35932
s35932 1
ext
2389
1.20 300
s35932 1
compl 300
179
248.45 s35932 1
stat
178
62.82 B
2492 0.4747
297
0
denoted by Tgiven
). Under column type we show the type
of the test sequence considered, where given corresponds
I
to the given test sequence T , ext corresponds to Text
,
I
I
compl corresponds to Tcompl , and stat corresponds to Tstat .
Under column len we show the length of the test
I
I
sequence Ttype
. If the last vectors in Ttype
do not detect
any faults, we do not include them when defining the
sequence length. Under column DIFF we show the size
I
of DIFF (Ttype
,B ). Under column rtime we show the nor-
I
malized runtime for the step that resulted in Ttype
. This
always includes fault simulation of the sequence. The runtime is normalized through division by the runtime for
simulating the given test sequence T . Since most of the
effort of the proposed procedure consists of fault simulation, normalization gives an indication of this effort. For
static test compaction there are significantly faster implementations, which we do not use here.
For the given and for the compacted test sequences
I
T and Tstat
we show under column storage the number of
bits required for storing the sequence. Storage requirements were discussed in Section II. We enter a C to indicate that conventional storage requires fewer bits, and a B
to indicate that storage based on the background vector
requires fewer bits. We then show the smaller of the two
I
values. For the final compacted test sequence Tstat
we
also show the storage requirements as a fraction of the
storage requirements for the given test sequence.
From Tables II and III it can be seen that for all the
circuits, at least one iteration of the proposed procedure
reduces the storage requirements of T .
The extension step results in an increase in DIFF .
This is mainly due to the introduction of random values
through the subsequence V . However, the complementation step is able to reduce DIFF significantly. Static test
compaction reduces DIFF slightly. Overall, comparing T
I
and the final test sequence Tstat
, the reduction in DIFF is
significant. The effect on storage requirements is
significant as discussed next.
For the given test sequence it is always preferable to
use the conventional storage scheme that requires nL bits.
For the modified test sequence it is almost always preferable to use the storage scheme based on the background
vector. This is due to the relatively small number of
I
entries in DIFF (Tstat
,B ). The storage requirements of
I
Tstat , based on the background vector, are significantly
lower than the conventional storage requirements for T .
Static test compaction is mostly important for
reducing the test sequence length without increasing the
I
size of DIFF . In several cases, the length of Tstat
is lower
than the length of T . This implies that the modification of
T also contributes to the ability to compact it. However,
the reduction in storage requirements is mostly due to the
use of the background vector B , and the storage requirements are reduced significantly even in the cases where
the test length is increased.
VI. CONCLUDING REMARKS
We described a storage scheme for functional test
sequences that uses background vectors. A test sequence
T is stored by storing only the differences between its test
vectors and a background vector B . We described a procedure for computing B for a given test sequence T . We
also described a procedure that modifies T so as to reduce
TABLE III
RESULTS FOR ITC-99 BENCHMARKS
len
ratio
circuit I
type
DIFF
rtime storage
0 given 168
b04
764
1.00 C
2016 b04
775
2.32 1 ext
335
b04
206
385.06 1 compl 335
b04
192
50.41 C
1608 0.7976
1 stat
134
b08
0
given
415
1791
1.00
C
4150 b08
1
ext
831
1804
2.00
b08
1
compl
831
63
234.42
b08
1
stat
314
61
34.46
B
732
0.1764
b10
0
given
190
904
1.00
C
2280 b10
917
3.39 1 ext
381
b10
103
466.82 1 compl 381
b10
102
59.32 B
1122 0.4921
1 stat
120
0 given 554
b11
1689
1.00 C
4432 b11
1702
3.63 1 ext
1109
b11
183
548.97 1 compl 1096
b11
97
152.43 B
1164 1 stat
295
2 ext
850
b11
113
3.51 2 compl 850
b11
87
73.52 b11
2
stat
292
86
78.97
B
1032
b11
3
ext
847
94
3.69
b11
3 compl 847
85
45.88 b11
3 stat
292
85
35.13 B
1020 0.2301
its storage requirements with respect to B . We presented
experimental results to demonstrate that, using a single
background vector B , it is possible to modify T such that
it differs from B only in a small number of entries. Consequently, storage of T reduces to storage of a small number
of primary input and time unit indices. This reduced
significantly the number of bits required for storing T .
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
[22]
[23]
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