E. T. TELECOMUNICACIONS
1BT4
DIGITAL ELECTRONICS
29/10/2008
Prof. F. J. Sànchez i Robert
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First minimum control: 25 min. Grades will be available by November 3
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Questions about the exam: WD:17 h – 19 h; TH: 17 h – 19 h; FR: 10 h-12h
VERY IMPORTANT: Draw a general schematic or plan, develop the exercise and justify the results always explaining
what are you doing
Minimum 3
In Fig. 1 we show the internal logic circuitry supplied by the manufacturer of the 74LS153 chip and its truth table.
Using data from the electrical characteristics in Fig. 2, deduce:
a) IN-OUT transfer curve showing HI and LO voltage values and the corresponding HI and LO noise margins for
the 74LS (Low-Power Schottky TTL) logic family. Explain the meaning of the logic margins.
b) The chip’s static power consumption assuming that output levels for any gate are equally probable events.
c) The chip’s maximum frequency of operation where you have to take always the worse case
----------------------------d) In addition to the above questions, explain the internal structure and operation of a CMOS NAND gate
Fig. 1 The 74LS153 Dual 4-line to 1-line multiplexer
Fig. 2 Electrical characteristics for a single LS logic gate