Instruction Set Architecture (ISA)
MIPS review
(Ch: 2.1- 2.7, 2.10 4th ed)
Instructions: Language of the Computer
Dr. Khaled El-Ayat
Jul-17
Intro & ISA.1
RISC vs CISC review
• RISC -- Reduced Instruction Set Computer  performance
– fixed instruction length
– load/store architecture
• all operands of ALU instructions must be in registers
– limited addressing modes & operations  fewer instructions
• Implies
–
–
–
–
larger register file
longer program
good for pipelining
simpler control
• CISC: Complex Instruction Set Computer variable instructions
Jul-17
Intro & ISA.2
CISC Ex: 80x86 Registers
Name
31
0
Use
EAX
GPR 0
ECX
GPR 1
EDX
GPR 2
EBX
GPR 3
ESP
GPR 4
EBP
GPR 5
ESI
GPR 6
EDI
GPR 7
EIP
EFLAGS
CS
Code segment pointer
SS
Stack segment pointer (top of stack)
DS
Data segment pointer 0
ES
Data segment 1 pointer
FS
Data segment 2 pointer
GS
Data segment 3 pointer
Instruction
pointer (PC)
Condition codes
Jul-17
Intro & ISA.3
CISC Ex: x86 Instructions have Variable
lengths!
a. JE EIP + displacement
4
4
JE
8
Condition Displacement
b. CALL
32
8
CALL
c. MOV
Offset
EBX, [EDI + 45]
6
1 1
MOV
d w
8
r-m
postbyte
8
Displacement
d.PUSH ESI
5
3
PUSH
Reg
e. ADD EAX, #6765
4
3
ADD
1
32
Reg w
Immediate
f.TEST EDX, #42
Jul-17
7
1
TEST
w
8
Postbyte
32
Immediate
Variability is an issue, but is solved by MicroArchitecture on all x86 CPUs
Intro & ISA.4
Instruction Set Architecture: What Must be Specified?
• Instruction Format or Encoding
•
•
•
•
Location of operands and result
Data type and Size
Operations
Successor instruction
– jumps, conditions, branches
Jul-17
Intro & ISA.5
Typical Operations (rev)
Data Movement
Load (from memory)
Store (to memory)
memory-to-memory move
register-to-register move
input (from I/O device)
output (to I/O device)
push, pop (to/from stack)
Arithmetic
integer (binary + decimal) or FP
Add, Subtract, Multiply, Divide
Shift
shift left/right, rotate left/right
Logical
not, and, or, set, clear
Control (Jump/Branch)
unconditional, conditional
Subroutine Linkage
call, return
Interrupt
trap, return
Synchronization
test & set (atomic r-m-w)
String
Graphics (MMX)
search, translate
parallel subword ops (4 16bit add)
Jul-17
Intro & ISA.6
Basic ISA Classes (rev)
Accumulator (1 register):
1 address
add A
acc acc + mem[A]
Stack:
0 address
tos tos + next
add
General Purpose Register :
2 address
add A B
3 address
add A B C
Load/Store:
3 address
add Ra Rb Rc
load Ra Rb
store Ra Rb
EA[A] EA[A] + EA[B]
EA[A] [B] + EA[C]
Ra Rb + Rc
Ra mem[Rb]
mem[Rb] Ra
Registers faster than memory, easier for compiler, less mem traffic
Jul-17
Intro & ISA.7
MIPS R3000 review: Registers
• Registers--32 general purpose registers
– $zero (0) : 0
Register $0 - $31
• 3 special purpose registers
• PC: program counter
• Hi, Lo for multiply and divide
• Word length=32 bits
• In memory: byte addressable
PC
Hi
Lo
Jul-17
Intro & ISA.8
MIPS Instruction Formats = 3
layout of instruction
• 3 formats:
R-type (regular)
OP
rs
rt
I-type (Immediate)
OP
rs
rt
J-type (Jump)
OP
rd
sa
funct
immediate
Target
• R-type: 6 fields
Jul-17
–
–
–
–
–
–
op: operation code (6 bits)
rs: 1st register source operand (5)
rt: 2nd register source operand (5)
rd: register destination (5)
sa: shift amount (5)
function: select the variant of operation in op field (6)
Intro & ISA.9
Instruction Format::R-Type
• Example: add $8, $17, $18
OP
rs
rt
rd
sa
funct
OP=00, FUNC=40
• Other R-type instructions
sub $1, $2, $3
slt $1, $2, $3
jr $ra(31)
#jump register, for returning to the
calling procedure
Jul-17
Intro & ISA.10
Instruction Format/I-type
OP
rs
rt
immediate
• 4 fields, 32 bits
• Immediate (address ) field: 16 bits, holds a constant
• Example: load word -- lw $s1, 50($s2)
lw $s1, 48($s2)
# $s1 = memory [$s2+48]
• Other I-type inst.
add immediate -- addi $8, $9, 100
branch on equal -- beq $1, $2, 25: goto (PC+4)+100 if
$1=$2
Jul-17
Intro & ISA.11
Instruction Format/J-Type
•
•
•
•
OP
2 fields: 32 bits
op: 6 bits
address field: 26 bits
Example: j 200
# go to location f(4*200)
Target
• Other J type inst.:
jal 200 # jump & link, goto location f(4*200)
$31(ra)= PC + 4
Jul-17
Intro & ISA.12
Jump Instruction
Psuedo direct addressing
j
label
#go to label
• Instruction Format (J Format):
op
26-bit address
26
00
32
4
PC
32
Jul-17
Intro & ISA.13
MIPS Addressing Modes fyi
• Register addressing
– operand is in a register
e.g. add $8, $19, $18
• Base or displacement addressing
– operand: at memory location reg. + constant (base)
e.g. lw $8, 200($19)
• Immediate addressing
– operand: constant, in inst.
e.g. addi $8, $8, 4
• PC-relative addressing
– address = (PC) + constant in inst.
e.g., bne $8, $21, Exit
• Pseudodirect addressing: jump address = PC(31-28)
(concatenated with) jump constant*4
Jul-17
Intro & ISA.14
MIPS Addressing Mode Summary fyi
1. Immediate addr essing
op rs rt
Immediate
2. Register addr essing
op rs rt
rd
. . .funct
Registers
Register
3. Base addr essing
op rs rt
Address
Register
Memory
+
4. PC-r elative addr essing
op rs rt
Address
PC
Byte
Halfwor
d
W ord
Memory
+
W ord
5. Pseudodir ect addr essing
op
Addr ess
Memory
PC
W ord
Jul-17
Intro & ISA.15
MIPS Conditional Branch Instructions
bne $s0, $s1, Lbl #go to Lbl if $s0$s1
beq $s0, $s1, Lbl #go to Lbl if $s0=$s1
– Ex:
if (i==j) h = i + j;
bne $s0, $s1, Lbl1
add $s3, $s0, $s1
...
Lbl1:
• Instruction Format (I format):
op
rs
rt
16 bit offset
• Target Address = PC +4 + (offset * 4)
Jul-17
Intro & ISA.16
More Branch Instructions
• Can use slt, beq, bne, and the value 0 in register
$zero to create other conditions
– less than
slt
bne
blt $s1, $s2, Label
$at, $s1, $s2
$at, $zero, Label
– less than or equal to
– greater than
– great than or equal to
#$at set to 1 if
# $s1 < $s2
ble $s1, $s2, Label
bgt $s1, $s2, Label
bge $s1, $s2, Label
• Such branches are included in the instruction set as pseudo
instructions - recognized (and expanded) by the assembler
Jul-17
Intro & ISA.17
MIPS Immediate Instructions
• Small constants are used often in typical code
addi $sp, $sp, 4
slti $t0, $s2, 15
• Machine format (I format):
op
rs
rt
#$sp = $sp + 4
#$t0 = 1 if $s2<15
16 bit immediate
I format
• Constant kept inside the instruction
– Immediate format limits values to the range +215–1 to -215
Jul-17
Intro & ISA.18
LUI used for 32-bit Constants
• To load a 32 bit constant into a register, two instructions
• "load upper immediate" instruction LUI
lui $t0, 1010101010101010
16
0
8
1010101010101010
• Then must get the lower order bits right, use
ori $t0, $t0, 1010101010101010
1010101010101010
0000000000000000
0000000000000000
1010101010101010
1010101010101010
1010101010101010
Jul-17
Intro & ISA.19
How shift instructions are implemented
Two kinds:
logical-- value shifted in is always "0"
"0"
msb
lsb
"0"
arithmetic-- on right shifts, sign extend
msb
lsb
No arithmetic Left Shift – Overflow result
Note: these are single bit shifts. A given
instruction might request 0 to 32 bits to be shifted!
Jul-17
Intro & ISA.20
Subroutine Calls & Stacks
Stacking of Subroutine Calls & Returns and Environments:
A
A:
CALL B
A B
B:
CALL C
A B C
C:
RET
A B
RET
A
Some machines provide a memory stack as part of the architecture (e.g., VAX)
Sometimes stacks are implemented via software convention (e.g., MIPS)
Some machines provide stack support in hardware (Embedded processor)
Jul-17
Intro & ISA.21
MIPS: Software conventions for Registers
0
zero constant 0
16 s0 callee saves
1
at
. . . (callee must save)
2
v0 expression evaluation &
23 s7
3
v1 function results
24 t8
4
a0 arguments
25 t9
5
a1
26 k0 reserved for OS kernel
6
a2
27 k1
7
a3
28 gp Pointer to global area
8
t0
...
15 t7
reserved for assembler
temporary (cont’d)
temporary: caller saves
29 sp Stack pointer
(callee can clobber)
30 fp
frame pointer
31 ra
Return Address (HW)
Jul-17
Intro & ISA.22
MIPS ISA So Far
Category
Arithmetic
(R & I
format)
Data
Transfer
(I format)
Cond.
Branch (I
&R
format)
Uncond.
Jump
(J
&R
Jul-17
format)
Instr
Op Code
Example
Meaning
add
0 and 32
add $s1, $s2, $s3
$s1 = $s2 + $s3
subtract
0 and 34
sub $s1, $s2, $s3
$s1 = $s2 - $s3
add immediate
8
addi $s1, $s2, 6
$s1 = $s2 + 6
or immediate
13
ori $s1, $s2, 6
$s1 = $s2 v 6
load word
35
lw
$s1, 24($s2)
$s1 = Memory($s2+24)
store word
43
sw $s1, 24($s2)
Memory($s2+24) = $s1
load byte
32
lb
$s1, 25($s2)
$s1 = Memory($s2+25)
store byte
40
sb
$s1, 25($s2)
Memory($s2+25) = $s1
load upper imm
15
lui
$s1, 6
$s1 = 6 * 216
br on equal
4
beq $s1, $s2, L
if ($s1==$s2) go to L
br on not equal
5
bne $s1, $s2, L
if ($s1 !=$s2) go to L
set on less than
0 and 42
slt
if ($s2<$s3) $s1=1 else
$s1=0
set on less than
immediate
10
slti $s1, $s2, 6
if ($s2<6) $s1=1 else
$s1=0
jump
2
j
2500
go to 10000
jump register
0 and 8
jr
$t1
go to $t1
jump and link
3
jal
2500
go to 10000; $ra=PC+4
$s1, $s2, $s3
Intro & ISA.23
MIPS arithmetic instructions fyi
Instruction
add
subtract
add immediate
add unsigned
subtract unsigned
add imm. unsign.
multiply
multiply unsigned
divide
Example
add $1,$2,$3
sub $1,$2,$3
addi $1,$2,100
addu $1,$2,$3
subu $1,$2,$3
addiu $1,$2,100
mult $2,$3
multu$2,$3
div $2,$3
divide unsigned
divu $2,$3
Move from Hi
Move from Lo
mfhi $1
mflo $1
Meaning
$1 = $2 + $3
$1 = $2 – $3
$1 = $2 + 100
$1 = $2 + $3
$1 = $2 – $3
$1 = $2 + 100
Hi, Lo = $2 x $3
Hi, Lo = $2 x $3
Lo = $2 ÷ $3,
Hi = $2 mod $3
Lo = $2 ÷ $3,
Hi = $2 mod $3
$1 = Hi
$1 = Lo
Comments
3 operands; exception possible
3 operands; exception possible
+ constant; exception possible
3 operands; no exceptions
3 operands; no exceptions
+ constant; no exceptions
64-bit signed product
64-bit unsigned product
Lo = quotient, Hi = remainder
Unsigned quotient & remainder
Used to get copy of Hi
Used to get copy of Lo
Jul-17
Intro & ISA.24
MIPS logical instructions
Instruction
and
or
xor
nor
and immediate
or immediate
xor immediate
shift left logical
shift right logical
shift right arithm.
shift left logical
shift right logical
shift right arithm.
Example
and $1,$2,$3
or $1,$2,$3
xor $1,$2,$3
nor $1,$2,$3
andi $1,$2,10
ori $1,$2,10
xori $1, $2,10
sll $1,$2,10
srl $1,$2,10
sra $1,$2,10
sllv $1,$2,$3
srlv $1,$2, $3
srav $1,$2, $3
Meaning
$1 = $2 & $3
$1 = $2 | $3
$1 = $2 $3
$1 = ~($2 |$3)
$1 = $2 & 10
$1 = $2 | 10
$1 = ~$2 &~10
$1 = $2 << 10
$1 = $2 >> 10
$1 = $2 >> 10
$1 = $2 << $3
$1 = $2 >> $3
$1 = $2 >> $3
Comment
3 reg. operands; Logical AND
3 reg. operands; Logical OR
3 reg. operands; Logical XOR
3 reg. operands; Logical NOR
Logical AND reg, constant
Logical OR reg, constant
Logical XOR reg, constant
Shift left by constant
Shift right by constant
Shift right (sign extend)
Shift left by variable
Shift right by variable
Shift right arith. by variable
Jul-17
Intro & ISA.25
MIPS jump, branch, compare instructions
Instruction
Example
Meaning
branch on equal beq $1,$2,25
if ($1 == $2) go to PC+4+100
Equal test; PC relative branch. Note: Offset field = 25
branch on not eq. bne $1,$2,25
if ($1!= $2) go to PC+4+100
Not equal test; PC relative Note: Offset field = 25
set on less than slt $1,$2,$3
if ($2 < $3) $1=1; else $1=0
Compare less than; 2’s comp.
set less than imm. slti $1,$2,100 if ($2 < 100) $1=1; else $1=0
Compare < constant; 2’s comp.
set less than uns. sltu $1,$2,$3
if ($2 < $3) $1=1; else $1=0
Compare less than; natural numbers
set l. t. imm. uns. sltiu $1,$2,100 if ($2 < 100) $1=1; else $1=0
Compare < constant; natural numbers
jump
j 2500
go to 10000
Jump to target address Note: jump field = 2500
jump register
jr $31
go to $31
For switch, procedure return
jump and link
jal 2500
$31 = PC + 4; go to 10000
For procedure call. Note: jump field = 2500
Jul-17
Intro & ISA.26