Microprocessor-based systems
Course 2
General structure of a computer
1
Components of a computer system
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Classic computer model (J. von Neumann)
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Control unit (CU)
Arithmetical and logical unit (ALU)
Memory (M)
Input device(s) (ID)
Output device(s) (OD)
M
Data and
program
input
D
I
CU
ALU
D
E
Data
output
CPU=CU+ALU
Central Processing Unit
2
Components of a computer system

μP
Microprocessor-based computer
system – a bus-based system
Memory
Memory
I/O Interface
I/O Interface
I/O Interface
3
The Central Processing Unit (CPU)
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Control Unit (CU)
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Responsible for:
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CPU
CU
PhG
It is a sequential circuit (state automatom)
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ALU
Usually it is a combinational circuit
General purpose registers (GR)
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PC
SR
Arithmetic: +,-,/,*, modulo, comparisons
Logic: SI, SAU, NU,
Shifts and rotations
Registers
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RI
Executes arithmetical and logical operations:
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CG
ID + CCB
The Arithmetical and Logical Unit (ALU)
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Instruction fetch (read)
Instruction decoding (interpretation)
Generation of command signals needed to
execute the instruction
Holds data
Take part in arithmetic and logic operations
Special purpose registers ():
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Addressing registers
Status register
Test registers
Control registers
GR
R1
R2
…
Rn
System Bus
4
Control Unit (CU)
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The brain of the computer
It is composed of:
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Clock generator (CG)
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Phase generator (PhG)
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PhG
PC
IR
Address
Instructions
ID + CCB
SR
Commands
Keeps the current instruction
Program counter PC
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Interpret the instructions and generate
command signals needed for instruction
execution
Instruction register IR
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CG
Generates the phases needed for
instruction execution
The Instruction Decoder (ID) and the
Command and Control Block (CCB)
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Generates the clock (synchronization)
signal
UC
Keeps the address of the next
instruction (to be executed)
(Program) Status Register (SR)
5
Arithmetical and Logical Unit
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Ac – Accumulator register
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Keeps one of the operands
and the result
R – register for the 2nd
operand
SR Status register
n
n
R
Ac
n
n
Operation
ALU
n
SR
6
Arithmetical and Logical Unit
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One bit adder with carry
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Si = Ai + Bi + Ti-1
Ci = Ai*Bi +Ci-1*(Ai + Bi)
Ti-1
Si
Ai
Bi
Ci
7
n bits adder
Bn-1
An-1
B1
n-1
Cn-1
B0
1
Cn-2
Sn-1
A1
C1
A0
0
C0
S1
C-1
S0
8
Adding operation with 2 registers
Step
Operation
Commands
1
Clear A
Ad = 0, CLKA = П (impuls)
Transfer D → B (operand 1)
CLKB = П
2
Transfer B → A , D → B (operand 2)
3
A←A+B
Ad = 1, CLKA = П, CLKB = П
Ad = 1, CLKA = П
Dn-1
D1
D0
Bn-1
B1
B0
n-1
A
n-1
1
A1
0
A0
CLKB
Ad
CLKA
9
Circuit for adding and subtraction in 2th
complement
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For adding: Ad/Sub = 0
For subtraction the second operand is complemented
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Ad/Sub=1
Dn-1
Bn-1
Tn-1
n-1
A
n-1
T1
D1
D0
B1
B0
1
A1
T0
CLKB
Ad / Sub
0
A0
CLKA
10
Logical unit with 4 operations
Ai
Bi
MUX 4:1
Ci
Ai-1
Bi-1
MUX 4:1
Operation
code
Ci-1
11
Multiply operation
1100 * 12 *
1010
10
Modified multiply operation:
0000
1100
0000
1100
“0” →
“1” →
1111000 = 78H = 120
“0” →
“1” →
00000000
0000000 0
1100
0001100 0
000110 00
00011 000
1100
1111 000
Acumulator (AC)
Shift right
Adding
Partial product
Shift right
Shift right
Adding
Final product
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Implementation of the multiply
operation
X
BS
Bn-1
...
B1
B0
 (n+1)
QS
AS
An-1
...
A1
A0
Q n-1
...
Write
Q0
Y
Write
Shift right
Clear
Q1
Test
Command Device
Shift right
Write
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Multiply algorithm
1.
2.
3.
Write the operands into the registers B ← X, Q
← Y, clear the accumulator A ← 0
Complement the operands if they are negative
Test Q0
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4.
5.
6.
Q0 = 0, shift A and Q to the right
Q0 = 1, add A = B + A and shift A and Q to the
right
Repeat step 3 until Yn-1 get into Q0. In the last
step the shift is not necessary
AS = BS + QS
Complement the result if AS = 1
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Division circuit
X
QS
AS
An-1
A1
...
A0
Ad / Sc
Sum, Diference
BS
Bn-1
B1
...
Q n-1
...
Q1
Q0
Control device
B0
Y
15
Division algorithm
1. Load the first operand in registers A and Q
Load the second operand in register B
2. Memorize AS + BS in QS. If
AS = 1, complement A, Q
BS = 1, complement B
3. Tests:
a. A ≥ B, overflow
b. B = 0, division by 0
c. A = 0 and Q < B, result = 0
4. Shift A, Q to the left and put 0 in Q0
5. Subtract B from A and put the result in A. If
AS = 0, shift left A, Q and put 1 in Q0
AS = 1, add B to A, shift left A, Q and put 0 în Q0
6. Repeat step 5 for n times
7. Round the result: if A ≥ B, add 1 to Q
8. If QS = 1 complement register Q
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Adding in floating point representation
1.
2.
Load the operands into registers
Compare the exponents (5 cases):
ex = ey, add mantissas and copy the exponent
ex > ey and (ex – ey) < mantissa’s bits, than my is aligned by
shifting to the rights with ex-ey positions and than add mx
with my
ex >> ey and (ex – ey) ≥ mantissa’s bits, than copy X into the
result
ex < ey şi (ey – ex) < mantissa’s bits, than mantisa mx is aligned
by shifting to the rights with ey-ex positions and than add
mx with my
ex << ey şi (ey – ex) ≥ mantissa’s bits, than copy Y into the
result
3. Normalize the result. Test the bits around the decimal
point and if necessary shift the mantissa to the right or
to the left and increment or decrement the exponent
17
Adder circuit for floating point numbers
X
Shift
A
S
exp
mantissa
Load
Increment
Exp A
Control device
Σ
Increment
B
S
exp
mantissa
Y
Exp B
Shift
Load
18
Multiply and division in floating point
representation
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Multiply is made as follows:
add the exponents
multiply the mantissas
normalize the result
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Division is made as follows:
subtract exponents
divide mantissas
normalize the result
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A
S
exp
Inc/Dec A
mantissa A
Shift
Left/right A
Ad/ Sc
Comand device
Σ/Δ
mantissa B
B
S
Shift
left/right B
exp
Inc/Dec B
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Design of a simple computer
Design steps:
1. Establish the destination and the domain of use for the
computer;
2 Define the instruction set and instruction format;
3 Design the block scheme of the central processing unit;
4 Decompose instructions into micro-operations and phases;
5 Define the logical equations/functions for the microcommands;
6 Design the logical scheme for the PhG and CCB;
7 design the other modules: IR, PC, GR, ALU, SR, CG;
8 Design of memory modules;
9 Design of I/O interfaces;
10 Optimize the scheme through steps 2-9
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Simple computer:
Design steps
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Destination:
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General purpose computer
Special destination computers:
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High performance computers:
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embedded computers
signal processing computers
control systems
Parallel and distributed systems (GRID, Cloud, etc.)
Instruction set:
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Instruction format: (length and fields)
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Fixed:
Variable
Operation Types:
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Arithmetic
Logic
Transfer
Jump and branch
Stack operations, etc.
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