Digital Logic & Design
Dr. Waseem Ikram
Lecture No. 25
J-K flip-flop with Asynchronous Preset and
Clear inputs
PRE
J
3
1
Q
4
2
Q
CLK
K
CLR
Logic Symbol of a J-K flip-flop with
Asynchronous inputs
PRE
J
CLK
Q
J-K
Flip-Flop
K
Q
CLR
Truth table of J-K flip-flop with
Asynchronous inputs
Input
Output
CLR
PRE
Qt+1
0
0
Invalid
0
1
1
1
0
0
1
1
Clocked operation
Timing diagram of a J-K flip-flop with
Preset and Clear inputs
J
K
PRE
CLR
CLK
Q
t1 t2
t3 t4
t5
t6 t7
t8 t9
t10 t11
t12
t13 t14 t15 t16
Master-Slave flip-flop
J
3
1
7
5
Q
4
2
8
6
Q
CLK
K
MASTER
SLAVE
Truth table of the Master-Slave JK flip-flop
Input
Outpu
t
CLK
J
K
Qt+1
Pulse
0
0
Qt
Pulse
0
1
0
Pulse
1
0
1
Pulse
1
1
Qt
Timing diagram of a Master Slave J-K flipflop
J
K
CLK
Q
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Propagation Delay, clock to low-to-high
transition of the output
CLK
Q
tPLH
Propagation Delay, clock to highto-low transition of the output
CLK
Q
tPHL
Propagation Delay, preset to lowto-high transition of the output
PRESET
Q
tPLH
Set-up time for a D flip-flop
D
CLK
ts
Propagation Delay, clear to high-to-low
transition of the output
CLEAR
Q
tPHL
Hold time for a D flip-flop
D
CLK
th
Circuit diagram of a One-Shot
+V
C
R
Timing diagram of a One-Shot
Trigger
Output of
NOR gate
Input of
NOT gate
Output of
NOT gate
t1
t2
Timing diagram of a non
retriggerable One-Shot
Trigger
Output of
One-Shot
t1
t2
t3
t4
t5
t6
Timing diagram of a nonretriggerable One-Shot with ignored
triggers
Trigger
Output of
One-Shot
t1
t2
t3
t4
t5 t6 t7
t8
t9 t10
Recap

D flip-flop applications





Data Storage
Synchronizing Asynchronous Inputs
Parallel data Transfer
J-K flip-flop
J-K flip-flop applications




Sequence Detector
Frequency Divider
Shift Register
Counter
Asynchronous Inputs




J-K flip-flop with asynch. inputs (fig 1a)
Logic symbol asynch. J-K flip-flop (fig 1b)
Function table (tab1)
Timing diagram (fig 1c)
Master-Slave flip-flop

Master Slave flip-flop (fig 2a)


Function table (tab 2)
Timing diagram (fig 2b)
Operating Conditions

Flip-Flop Operating Conditions






Propagation delay (fig 3,4,5,6)
Set-up time (fig 7)
Hold Time (fig 8)
Max clock frequency
Pulse Width
Power Dissipation
Multivibrators

Mono-Stable Multi-vibrator (fig 9)


Non-Retriggerable (fig 10)
Retriggerable (fig 11)