Adaptive Noise Cancellation
System
A simple active noise cancellation system to counter a specific noise signal.
Prepared By: Irtaza Ahmed
Michael Foster
Michael Loper
Date: September 20, 2015
Table of Contents
Overview ....................................................................................................................................................... 1
Needs Statement ...................................................................................................................................... 1
Objective Statement ................................................................................................................................. 1
Description ................................................................................................................................................ 1
Marketing Picture ..................................................................................................................................... 2
Requirements Specifications......................................................................................................................... 3
Customer/Marketing Requirements ......................................................................................................... 3
Engineering Requirements........................................................................................................................ 3
Concept Selection ......................................................................................................................................... 5
Brief History .............................................................................................................................................. 5
Survey of Existing Systems/Components .................................................................................................. 5
Design............................................................................................................................................................ 6
Overall system and Subsystems................................................................................................................ 6
Figure 1: Level zero block diagram representing the FPGA, inputs, and outputs. .................. 6
Figure 2: Level one block diagram of the Virtex-5 FPGA. ........................................................... 9
Figure 3: Level three block diagram of a general DSP slice used as a Multiply Accumulate
Unit. .................................................................................................................................................... 10
External Hardware .................................................................................................................................. 10
Adaptive Algorithms ............................................................................................................................... 12
Figure 4: Stem plot of a sinusoidal signal ..................................................................................... 13
Figure 5: Block diagram of a third-order FIR filter implementation ........................................... 14
Figure 6: Top-level block diagram of the adaptive noise cancelling algorithm. ...................... 15
Circuits and Assemblies .......................................................................................................................... 16
Figure 7: Pin configuration of the microphone. ............................................................................ 16
Figure 8: Block diagram of the I2S hardware needed. ............................................................... 17
Figure 9: USB Controller on the Virtex-5. ..................................................................................... 18
Figure 10: Audio Codec on the Virtex-5. ...................................................................................... 19
User Interface and Controls .................................................................................................................... 19
Figure 11: User interaction state diagram. .................................................................................. 19
Figure 12: Prototype of user interface. ........................................................................................ 20
Engineering Standards ............................................................................................................................ 20
Multidisciplinary Aspects ........................................................................................................................ 20
Background ............................................................................................................................................. 21
Outside Contributors .............................................................................................................................. 21
Constraints and Considerations .................................................................................................................. 21
Extensibility ............................................................................................................................................. 21
Manufacturability ................................................................................................................................... 21
Societal Context ...................................................................................................................................... 22
Reliability................................................................................................................................................. 22
Health and Safety Issues ......................................................................................................................... 22
Economic Context ................................................................................................................................... 23
Intellectual Property ............................................................................................................................... 23
Cost Estimates ............................................................................................................................................. 24
Testing Strategy .......................................................................................................................................... 26
Risks ............................................................................................................................................................ 30
Algorithm ................................................................................................................................................ 30
Board ....................................................................................................................................................... 30
Interface .................................................................................................................................................. 30
Milestone Chart .......................................................................................................................................... 31
Appendices/References .............................................................................................................................. 33
Adaptive Noise Cancellation System
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Overview
Needs Statement
Noise cancellation is a thriving and popular industry in today’s society. As we
push forward in this modern era, technology is becoming an ever growing distraction
and hindrance in the flow of daily life. The need to unplug and disconnect becomes
evident. Noise cancellation headphones can help to provide that relaxing commute and
block out the uncomfortable noises surrounding travel via aircraft, trains, or even
automobiles.
Larger noise cancellation systems can also remove distracting
background noises to provide that perfect laboratory or educational working
environment. A small and affordable system is needed to counter unwanted noise
signals and to create a quieter and more comfortable environment for the customer.
Objective Statement
The objective of this project is to research, design, and implement an active
noise cancellation system that will be affordable to a general audience. The device will
produce signals to achieve destructive interference with an input signal. The input signal
will represent unwanted noise outside of a desired frequency range. The system will be
primarily designed for use with headphones, but it will be adaptable for use in more
complex applications such as a speaker system. One possible application of the
system would be a laboratory environment which contains noisy machines or power
tools. In this application, the system would be connected to a set of speakers in the
laboratory, and the system would counter the noise produced by the machines or tools.
Headphones could also be connected to the system, and it would function like a set of
noise cancelling headphones.
Description
Adaptive noise cancellation systems actively produce counter signals to block out
undesirable signals at specified frequencies or frequency ranges. The adaptive noise
cancellation system for this project will be built using two microphones, a headset, and a
Field Programmable Gate Array (FPGA). There will be one external microphone that
will take in the noise signal to be processed by the FPGA. The FPGA will then use the
FIR (finite impulse response) and LMS (least mean square) algorithms to attempt to
produce the necessary counteractive signal. The FPGA in turn sends the counter signal
to the headset. The signal from a feedback microphone in the headset will be used to
produce the next iterations of the algorithm until a desired noise signal degradation
threshold has been reached. If the system is used with a set of speakers, the feedback
microphone would be placed in the region where noise cancellation is desired.
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Marketing Picture
Adaptive Noise Cancellation System
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Requirements Specifications
Customer/Marketing Requirements
1. The system should be safe.
2. The system should be small.
3. The system should be affordable.
4. The system should correctly cancel all undesired sounds.
5. The system should use standard audio connectors.
6. The system should be easy to maintain and upgrade.
7. The system should be easy to move.
8. The system should be durable and have protection against damage.
9. The system should not produce much heat.
10. The system should have a simple interface.
11. The system should be aesthetically pleasing.
12. The system should be energy efficient.
13. The system should be able to accept input noise.
14. The system should reduce the volume of undesired sounds quickly.
Engineering Requirements
Marketing
Engineering Requirements
Requirements
10
A. User interface will consist of
a single on/off switch.
6
B. The design process will be
well-documented.
4,10
5,6
3
1,2,7,8,11
Justification
The system does not need to be
configured by the user.
Documentation is important for any
future work that may be done on the
project. It can also be used as a
resource for other projects.
C. Upon power up, the system This chosen frequency range signifies
will counteract noise signals
all the unwanted noise the system will
which fall between 40 Hz and need to counter-act. This range does
80 Hz.
not need to be configured by the user.
D. The output of the system
The 3.5 mm headphone jack is the
will be a 3.5 mm headphone
standard for many electronic devices.
jack.
E. The cost of the system will Keeping the cost of the system to
not exceed $1000 per
$1000 per unit will help make the
academic unit.
system more affordable and
marketable to customers.
F. The processor and all
Keeping the system enclosed in a case
internal connections must be that is about the size of the board used
enclosed in a hard case with
will ensure that the system is safe,
dimensions no more than four small, easy to move, durable, and
inches larger than the
more aesthetically pleasing to the
dimensions of the FPGA on
customer.
each side.
Adaptive Noise Cancellation System
5,8
4
3,9,12
1,12
4
4,14
G. The system must contain
two microphones, an FPGA,
necessary wires, a headset,
and a hard case.
H. The microphones must be
able to detect frequencies in
the range from 20 Hz to 20
kHz.
I. The system must consume
less than 0.3 kWh on average.
J. The system must not
exceed a peak instantaneous
power usage of 10 W.
K. A drop in the volume of the
noise signal must be detected
by 85% of individuals who test
the system.
L. The delay between the point
at which the system is
powered on and the noise
signal is cancelled will not
exceed 3 seconds.
1,4
M. The volume of the counter
signal will not exceed 85 dB.
13
N. The system must be able to
interact with two microphone
inputs either through line
inputs or GPIO pins.
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The basic components are what the
system needs to work.
This is a basic need of the system so
that it can detect the noise signals
which must be countered.
With a low power consumption, the
product is more affordable. Low-power
systems also do not produce much
heat.
Putting a cap on the peak power usage
of the system will act as a safety
feature to keep it from tripping breakers
or drawing more than a desired amount
of power at any given point in time.
This will also ensure that the system
stays energy efficient.
The noise signal will not be completely
countered; however, a drop in volume
should be detectable by a customer
with average hearing capabilities.
If the delay is too long, there will be an
extended period of unpleasant ringing
while the signals are not 180 degrees
out of phase. If this period is
excessively long, it could become
unpleasant to the customer.
To produce a pleasant output sounds
the counter signal must be relatively
inaudible by humans. Also, the system
should never produce a sound that
could be painful or cause harm to the
customers’ ears.
This is a fundamental part of the
system’s operation. The system must
be able to take in the noisy signal and
have a feedback loop for the algorithm
to work.
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Concept Selection
Brief History
In the 1990s, personal active noise cancelling systems consisted of a pair of
headphones connected to a processing unit. This processing unit was either encased
in a hand-held module or it was integrated into a stationary object such as an armrest in
an airplane seat. Modern noise cancelling headphone designs are now embedding the
processors in the headphones. These processors could be high-end DSPs (Digital
Signal Processors) or ASICs (Application Specific Integrated Circuits).
Survey of Existing Systems/Components
Silentium is a company that specializes in noise cancellation systems and
solutions. One of its products is the “ActiveSilencer Enclosure.” This noise cancellation
device is specifically designed to minimize the noise pollution from servers by up to 10
dB without causing any thermal or cooling degradation. Silentium also has the “S-Cube
Development Kit” that is designed to allow an individual to create their own custom
noise cancellation solution. Silentium suggests the S-Cube can be used in applications
such as reducing fan noise or irritable noise created by electronics in general. This
system costs $4,500, which is well over the cost of our system. Silentium claims that its
products can cancel frequencies from low range signals up to 1800 Hz. Its systems can
also counteract multiple frequencies rather than just a single tone.
There are a wide array of noise cancellation headphones in today’s market.
There is a pair of MDR ZX110NC SONY headphones that claims to reduce up to 95
percent of ambient noise produced by the office, airplanes, and trains. These
headphones are at a low cost of around $40. These headphones are for the specific
use of providing comfort for travel. Most of the headphones on the market that are used
to give quality sound and combine the use of passive and active noise cancellation start
at $250.
Our system helps to provide an affordable solution to general noise cancellation.
The system we have proposed will cost less than many of the noise cancellation
systems available, while still providing the ideal quiet environment. Our device is
expandable beyond headphone application, but each system will be more affordable
than existing active noise cancellation systems.
‘
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Design
Most noise cancellation systems use microphones, FIR filters, cancellation
algorithms, and speakers or headphones. We will be following this model that has
succeeded in the past.
Figure 1 shows the two inputs and outputs for microphones and one output for
the headphones. The board will be programmed through a PC using the JTAG to USB
communication. The board will also be connected serially to the computer for testing
purposes, and oscilloscopes will be used on the microphone communication lines. The
inputs for the microphones will be the inputs and outputs for the bidirectional
communication required by I2S.
Figure 1: Level zero block diagram representing the FPGA, inputs, and outputs.
Overall system and Subsystems
Since we will not have the funds to produce an ASIC design, the only viable
processor solutions for this project are a DSP or an FPGA. One advantage of an FPGA
is that it can perform multiple operations at a time due to its use of parallelism, where a
DSP processor performs one instruction at a time. However, as filter order increases,
the delay in the FPGA increases due to register-to-register delay, and the speed
increase due to parallelism with be overcome. Research showed the tradeoff here and
compared an implementation of a filter of order ten implemented on an FPGA processor
versus on a DSP processor of similar specifications [8]. The DSP processor took 2.3 µs
Adaptive Noise Cancellation System
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to update the weights on the adaptive filter and the FPGA took 67 ns [8]. This
difference is astounding for a filter of order ten.
From research it is has been determined that we will require a filter order in the
range of 8 to 64 [8]. Most FPGAs will have the resources to do the computations for
filters of these orders faster than similarly specified DSPs. Also, if the chosen FPGA
has on-board DSP slices, it will produce the desired results very rapidly. For these
reasons, we have decided an FPGA will be the right fit for our implementation of an
adaptive noise cancellation system.
We also believe that an FPGA implementation will give our design a higher
degree of flexibility. This flexibility will become especially important if we are able to
expand the application of our design to noise cancellation in complex environments
such as small rooms. This complex implementation would likely require a large number
of parallel computations in order to counter complex combinations of noise signals in
real time.
There are a wide variety of FPGAs in today’s market. The following table was
produced by obtaining a subset of FPGAs that have successfully been used in existing
adaptive noise cancellation systems or projects.
Board
Number of
Multipliers
Slices
LUTs
DSP
Slices
Cost
Xilinx Virtex-2 Pro
XC2VP30
136 (18 x 18)
13,696
27,392
No
$1,799 or $399
(Academic)
Xilinx Virtex-5
XC5VLX110T
64 (25 x 18)
17,280
69,120
Yes
$2,199 or $799
(Academic)
Xilinx Spartan-3E
XC3S500E
(Starter Kit)
20 (18 x 18)
4,656
9,312
No
$199
ALTERA DE2
CYCLONE-II
EP2C5
13 (18 x 18)
2304 (est)
4,608
No
$137
NI cRIO-9104
96 (18x18)
14,336
28,672
No
$3,559
The consensus of the existing research is to use an LMS adaptive filtering
algorithm that utilizes FIR filters [2, 11, 13, 15, 16]. The desired FPGA must have
enough slices to hold a high order FIR filter implementation. The higher the filter order,
the more slices will be required. The desired FPGA must also be able to multiply and
add rapidly to perform the LMS filter iterations at a desired rate. From the research, it
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was determined that for a filter length of 512, around 1600 slices are needed for a board
with no dedicated DSP slices [2, 5, 8]. Dedicated DSP slices on an FPGA contain at
least one multiply and accumulate unit. These units are capable of performing
consecutive multiplication and addition operations quickly and efficiently. These units
will therefore directly aid in the speed of an LMS algorithm due to the numerous multiply
and accumulate operations required. The desired filter length will be based on the input
frequency range of the noise signals, which the system is capable of countering.
Generally, an FIR filter of order 8 to 64 was used in the successful projects to cancel a
60-Hz signal. This gives a range of around 180 to 330 slices required for the general
boards and even fewer slices needed for a board with dedicated DSP slices. The
research also suggests that the reduction of resources utilized by the board from using
DSP slices will reduce the total power consumption by up to 50% [8]. Speed is the most
important requirement our system needs, and the Xilinx Virtex-5 provides the extreme
speed and efficiency needed to satisfy all the system requirements while leaving room
to successfully grow into a more complex cancellation system.
Figure 2 shows that the FPGA will take in digitized data points from the external
MEMs based microphone and give them to the DSP slices inside the FPGA (The MEMs
microphones have analog to digital converters to give the digitized data desired.). The
FPGA will use the LMS algorithm to produce a series of coefficients, W N's, from the
input signal and the feedback signal. These coefficients will be given to the DSP slices
to perform calculations on the input signal to produce the counteractive signal. The
combination of the signals will be given to the audio codec, which sends the analog
version of the output signal out to the headphones. The other MEMs based microphone
inside the headset will act as a feedback system to send the signal back into the FPGA,
which will then use the LMS algorithm to generate, if necessary, the next iteration of the
coefficients to produce even less error. This process is repeated until the error reaches
the desired threshold. Both microphones use the I2S protocol to talk to the FPGA
through the GPIO pins. This produces the need for two microphones and one line
output for the headphones.
Adaptive Noise Cancellation System
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Figure 2: Level one block diagram of the Virtex-5 FPGA.
Figure 3 shows how the DSP slices can be set to easily multiply and accumulate
results, which is what is needed for the LMS algorithm to work efficiently. The DSP
slices will calculate the filter error from the new filter weights generated by the processor
and the input signal.
Adaptive Noise Cancellation System
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Figure 3: Level three block diagram of a general DSP slice used as a Multiply Accumulate Unit.
External Hardware
Two microphones are needed for the system, one to detect the noise, and
another to collect the feedback signal. Current noise cancelling headphone systems
include these microphones mounted on the inside and outside of the headphone earcup. The external microphone picks up the noise signals such as traffic or
conversations. The feedback microphone is placed inside an ear-cup of the
headphones to create a feedback loop for active noise control. In this project, the outer
noise detection microphone will be an external, handheld microphone. The table below
shows some of the microphones that are being used in the noise cancellation
applications today.
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Microphone
Frequency Response
Output SNR
High SPL Analog Microphone
6 Hz -20 kHz
Analog 63
Ultra-low current-low noise microphone
75 Hz - 16 kHz
Analog 64
Omnidirectional MEMS Microphone with 60 Hz - 15 kHz
Bottom Port
I2S
61
45 Hz – 20 kHz
I2C
65
Low-Noise Microphone
The best-suited microphone for this project is the Omnidirectional Microphone
with Bottom Port and I2S output from InvenSense. The frequency response and the
signal-to-noise-ratio (SNR) were two major factors in deciding which microphone would
work best for this project. Based upon our specifications, we decided that a microphone
with a frequency response from 60 Hz to 15 kHz would be sufficient. In addition, the
SNR should be around 60 dB to sufficiently pick up the sound of normal human voice
over three feet [31]. Therefore, the Omnidirectional Microphone from InvenSense was a
good match for this project. The microphone’s sensitivity to a sound source does not
change with the position of the source due to its omnidirectional nature. The I2S output
interface also allows the microphones to be connected directly to the FPGA without the
need for an audio codec in the system. Finally, the frequency response of this
microphone is between 60 Hz to 15 kHz, which is sufficient enough to produce an
accurate representation of the original sound.
The headphones needed for the noise cancellation system should have the
capability of handling a frequency response from 20 Hz to 20 kHz. The ear-cup of the
headphones should also be able to fit the feedback microphone. The table below
shows some of the headphones which were considered.
Headphones
Frequency
Response
Max Power
(mW)
Sensitivity
(dB)
Superlux HD668B Dynamic SemiOpen Headphones
10 Hz – 30 kHz
300
98
Superlux HD681
10 Hz – 30 kHz
300
98
Superlux HD661
10 Hz – 20 kHz
200
102
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The Superlux Dynamic Semi-Open Headphones have been chosen for this
project. They have the capability of reproducing frequency signals from 10 Hz to 30
kHz. This will allow them to produce an output signal with low noise distortion.
Moreover, since the microphone is only 4.72 mm x 3.76 mm x 1 mm, it should be able
to be hidden inside one of the headphones’ ear-cups.
Adaptive Algorithms
Adaptive noise cancellation algorithms are implemented in many different types
of products. These products range from small hearing aids to the large systems used in
vehicles such as cars or airplanes. Although these applications seem quite different,
the backbone of the algorithms is very similar. Two of the main algorithms which were
encountered during the research process were the IIR (infinite impulse response) filter
and FIR filter algorithms. The IIR filter algorithm is not often used in current products
[12]. After more research and development, however, this algorithm may prove to be
the best solution. The vast majority of the articles on adaptive noise cancellation found
during the research process relied solely upon the FIR filter algorithm. All of these
articles also used some variation of the LMS algorithm to allow the FIR filter to be
adaptive [2, 11, 13, 15, 16].
An algorithm must be selected based upon its ability to counter-act the expected
noise signals. All of the algorithms found during the research process seemed to be
capable of counter-acting input frequencies within the human audible frequency range,
20 Hz to 20 kHz. The algorithms were generally ranked by the speed at which they
could converge upon the frequency of the noise signal. In this project, the output
counter-signal can be muted at start-up until the algorithm converges. Therefore, the
start-up convergence delay should not be perceptibly long, but it is not required to be
imperceptible by the user. The speed at which the system reacts to impulsive noise
during normal operation could become an issue. The selected algorithm should have
the fastest possible convergence time given the resources available in the selected
processor.
The selected algorithm must have been previously documented and tested. In
order to deliver this product by the prescribed deadline, a large portion of the work on
this project must be allocated to the implementation process. Some research will be
necessary, but there is not a sufficient amount of time to develop and test a new
algorithm.
The FIR filter algorithm combined with the LMS algorithm has been selected for
this project. The extensive amount of available documentation for these algorithms
made them the optimal choice. These algorithms have been shown to be robust in
similar products. The LMS algorithm can also be expanded and improved for more
complex implementations.
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The success of this project relies heavily on a correct application of the FIR filter
and LMS algorithms. The remainder of this section will introduce the concepts and
mathematical computations behind these algorithms.
The input of the FIR filter algorithm is a continuous stream of sample amplitude
values. Figure 4 shows a sampled representation of a sinusoid signal. This “stem” plot
shows the spacing and values of the samples. The circles at the end of each stem
mark the amplitude value, which will be sent to the FIR filter.
Figure 4: Stem plot of a sinusoidal signal
The FIR filter algorithm calculates a new amplitude for the most recent sample.
This new amplitude is based on the value of the most recent amplitude and the
amplitude of several samples processed before the most recent sample. The number of
previous samples used in the calculation is called the order of the filter. A third order
filter would use Equation 1 to calculate the new amplitude value.
𝑦[𝑛] = 𝑊0 𝑥[𝑛] + 𝑊1 𝑥[𝑛 − 1] + 𝑊2 𝑥[𝑛 − 2] + 𝑊3 𝑥[𝑛 − 3]
(1)
In Equation 1, x[n] represents the most recent input sample, and x[n – 1]
represents the sample before the most recent sample. The updated sample amplitude
is represented by y[n]. The “W” values are the scaling factors. Notice that every term in
the FIR filter equation requires one multiplication and one addition. When an algorithm
is tuned for a specific computational application, the number of operations per iteration
Adaptive Noise Cancellation System
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is very important. The number of operations directly affects the overall speed of the
implementation. The order of the FIR filter, therefore, must be carefully selected in
order to meet the engineering requirements of the project. Research suggests that the
order of a FIR filter used in this type of application could be from eight to sixty-four [8].
In this project, the order of the filter will likely be set as a parameter, which can easily
be changed during testing.
Figure 5 shows a block diagram for a hardware implementation of a third-order
FIR filter.
Figure 5: Block diagram of a third-order FIR filter implementation
In an FPGA, flip-flops can be used as unit delay blocks, and MAC (multiply
accumulate) modules can be used for the multiplication and addition operations.
Multiplication operations will likely be slower in FPGAs that do not have available MAC
modules. These FPGAs would therefore need to use lower order FIR filters in order to
achieve the same computational speed as FPGAs with MAC modules.
If the filter did not need to be adaptive to the input signal, the “W” values could be
constants saved in a memory module. Adaptive filters, however, require an algorithm
Adaptive Noise Cancellation System
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which can adjust these scaling values until the system converges on the desired output.
The least mean square algorithm is commonly used for this function. Figure 6 shows a
top-level view of the full adaptive filter algorithm.
Figure 6: Top-level block diagram of the adaptive noise cancelling algorithm.
In Figure 6, x[n] represents the input signal from the noise source, and y[n]
represents the output counter-signal of the noise cancellation system. The error signal,
e[n], is taken from a sensor placed in the region where the noise is to be cancelled. The
LMS algorithm attempts to minimize the amplitude of the error signal by adjusting the
Wn scaling values. The standard form for the LMS algorithm is given in Equation 2.
𝑊[𝑛 + 1] = 𝑊[𝑛] + 2 ∗ µ ∗ 𝑒[𝑛] ∗ 𝑥[𝑛]
(2)
Notice that this standard form requires three multiplications and an addition.
Since multiplications can be computationally expensive, several variations of the
standard LMS have been developed which minimize the number of required
multiplications while maintaining an acceptable adaption speed. Two common LMS
variations are the sign-data least mean squares (SDLMS) and the sign-error least mean
squares (SELMS). The SDLMS algorithm replaces x[n] with the sign of x[n], and the
SELMS algorithm replaces e[n] with the sign of e[n]. The step size µ is often chosen to
be a small power of two in order to turn its multiplication operation into a simple bit shift.
Some articles also suggested that µ should vary with the input in order to improve
performance. Many descriptions of these types of modifications were found during the
research process [16]. Specific modifications were often mapped to specific types of
Adaptive Noise Cancellation System
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complex noise. For example, some suggested algorithm modifications specifically
targeted impulsive noise [14].
Since the exact algorithm performance requirements for this project are not yet
known, some experiments will need to be performed in order to find the level of
algorithmic complexity necessary to meet marketing requirement four. The selected
algorithm will also need to be tailored to exploit the strengths of the selected processor.
These strengths will be better understood after the results of the FPGA risk
investigation have been presented.
Circuits and Assemblies
An essential part of the project is to understand the pin configuration and the
functional descriptions of the microphone that will be used. Figure 7 shows the pin
configuration of the Omnidirectional MEMS Microphone.
Figure 7: Pin configuration of the microphone.
Pin 1 is a serial data clock used for I2S interface. Pin 2 is a serial data output pin that is
also used for I2S interface and requires a 100 kΩ pull-down resistor. This pin tri-states
when not actively driving the appropriate output channel. Pin 3 is a serial data-word for
I2S interface. Pin 4 is a left/right channel select. The microphone outputs its signal in
the left channel of the I2S frame when pin 3 is set low, and the microphone outputs its
signal in the right channel when pin 3 is set high. Pins 5, 6 and 9 are required to be
connected to ground on the PCB. Pin 7 is a VDD pin that is used to provide power
between 1.8V and 3.3V. The datasheet specifies that pin 7 should be decoupled to pin
6 with a 0.1µF capacitor. Pin 8 is a microphone enable. When set low (ground), the
microphone is disabled and put in power-down mode. When set high (VDD), the
microphone is enabled.
As can be seen in Figure 8, the microphones will communicate with the board
using the I2S protocol. Each microphone will be connected to GPIO pins on the board
Adaptive Noise Cancellation System
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by three wires: SCK (clock), WS (serial-data word select), and SD (output data pin).
There will also be a 100-kΩ pull down resistor on the SD wire.
Figure 8: Block diagram of the I2S hardware needed.
Figure 9 shows the schematic of the USB controller on the Virtex-5. These
GPIO pins will be used to connect the microphones to the FGPA. These pins could also
be configured to use the I2S protocol if needed. There are two pins dedicated for
communication purposes, pin 39 and 40. Pin 39 will act as the SCK clock for our I2S
communication, and pin 40 will act as the data communication pin. The data word
select will be connected to another of the GPIO clocks.
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Figure 9: USB Controller on the Virtex-5.
Figure 10 shows the schematic of the on-board Audio Codec of the Virtex-5
FPGA. This audio codec will use the line out to send the counter signal to the
connected headset. The schematic also shows two line-in inputs and two microphone
inputs. This provides the ability to use standard microphones through the audio codec if
needed.
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Figure 10: Audio Codec on the Virtex-5.
User Interface and Controls
Figure 11: User interaction state diagram.
The user interface is designed to be very simple as can be seen from Figure 11.
The user will be to take the product as is and press a single button to turn the system
on. The system is designed to work when powered on based on the programming done
in factory. If something were to go wrong or the system were to freeze, the user has
access to another button to reset the system. The system will reset within ten seconds
Adaptive Noise Cancellation System
P a g e | 20
upon the reset button being pressed. The user can press the same switch that powered
on the system to power off the system when desired.
Figure 12: Prototype of user interface.
A prototype of the system can be seen in Figure 12. This prototype
demonstrates the basic user interface. The actual placement of the buttons may be
different in the finished product. The casing will also have holes to allow for the power
cable, headphones, and the wires connecting the microphones.
Engineering Standards
I2S is an electrical serial bus interface that is used for connecting digital audio
devices together. The I2S design handles audio data separately from a clock, which
precludes time-related errors that cause jitter. The I2S design consists of three serial
bus lines: a line with two time-division multiplexing (TDM) data channels, a word select
line, and a clock line.
We will be using a 3.5-mm headphone jack to interact with the product’s provided
headset. The tip of the 3.5-mm male jack from the headset represents left audio, the
center portion represents right audio, and the base represents ground.
We will also be using a 120-Vrms, 60-Hz AC source through an AC adapter to
provide the 5 V necessary to power the FPGA through a DC barrel jack.
We will be using two main software tools, the Xilinx ISE tool suite and MATLAB.
MATLAB will be used to simulate the algorithm and provide us with simulation results
that can be used for testing and debugging purposes. The Xilinx ISE tool suite will be
used to write the algorithm in VHDL, place the algorithm on the board, and assign the
input and output pins.
Multidisciplinary Aspects
This project helps to incorporate our foundation of Computer Engineering and our
understanding of Electrical Engineering fundamentals to produce a working adaptive
noise cancellation system. We will utilize our Electrical Engineering circuit design
knowledge to design and test a printed circuit board in order to use the MEMs based
microphones. We will use surface mounting techniques to place and solder the
components needed to have the microphones function properly. Our knowledge and
Adaptive Noise Cancellation System
P a g e | 21
understanding of digital signal processing will help us design and create the necessary
FIR filters for adaptive noise cancellation. Our Computer Engineering background will
be useful for designing optimal VHDL descriptions of state machines for programming
various portions of the FPGA.
Background
The Digital System Design, VHDL, Digital Signal Processing, and Interface and
Digital Electronics courses helped give the strong foundation of knowledge required to
implement this project. Members of the project team also have recreational and work
experience in the implementation of digital designs in FPGAs.
Outside Contributors





Dr. Marcin Lukowiak has donated a Virtex-5 FPGA until the end of the
project.
Dr. David Borkholder has given us a supply of MEMs based microphones.
Rick Tolleson has donated a pair of Superlux Dynamic Semi-Open
headphones until the end of the project.
Jeffrey Lonneville will be aiding in the surface mounting process for the
microphones and other surface mounted parts.
Dr. Vincent Amuso has offered his services to act as an audio consultant
for the duration of our project.
Constraints and Considerations
Extensibility
The project is about designing a system to counteract single tone frequencies of
a desired range. The project may expand to counteracting multiple tones inside the
desired frequency range for the microphone and headset scenario. This will be
adaptable to work in a scenario using a microphone and speakers like the ones used in
cars or airplanes. The system may also be adaptable in the sense that it can be
optimized to be used well in an array of environments, from a noisy lab environment to a
noisy street environment. The portability, competitive price, and ease of use of the
system could make it a viable option for almost any scenario where one would want to
use adaptive noise cancellation.
Manufacturability
The system does not have very many components. Each system contains an
FPGA, two microphones, and a headset. Once we have created the PCB layout for the
microphones, the system will be very easy to manufacture on a large scale. The
manufacturing process will consist of ordering the PCB boards, doing the surface
mounting, programming the FPGAs, and placing the systems in a hard encasing. Once
this is done, each system should go through a series of defined tests. This carefully
Adaptive Noise Cancellation System
P a g e | 22
targeted testing will ensure maximum reliability with minimal testing required. Once
they have passed these tests, they will be in a shippable state. The cost of each unit
will be under $1000 dollars for a customer in academia and $2500 for non-academic
customers. The cost estimate will be reduced when the systems are manufactured in
bulk. Our system as a whole will be very easily manufactured at a minimal cost while
maintaining high system reliability.
Societal Context
Noise cancellation applications are growing in popularity in our society in recent
years. These systems help to reduce or remove distractions from an individual looking
to concentrate on other tasks. Noise cancellation can provide a quieter work
environment or can provide that extra external noise reduction that gamers seek.
Unfortunately, noise cancellation systems are not cheap, whether it is a headset or a full
system with speakers. Our active noise cancellation system will give people the
opportunity to take advantage of such systems for a reasonable price.
Passive noise cancellation systems are also growing in popularity. These
nonintrusive designs can be implemented into the architecture of a home while keeping
the home aesthetically pleasing. Many of these designs are used to cancel railroad
noises or general traffic noises in congested areas.
Reliability
The reliability of the full system is determined by the individual reliability of the
components and interconnections. The FPGA, microphones, and headphones have
been deemed reliable by their respective manufacturers. Since this system will not be
subjected to any unusual environmental conditions, the lifetime of these components
will be the same as any marketable processing units or audio electronics.
The PCB will be manufactured by a reputable manufacturer with proven
reliability, and the components will be soldered onto the PCB by an experienced
engineer using state-of-the-art equipment. All internal and external PCB connections
will be thoroughly tested before it is integrated into the system.
The FPGA board contains an integrated headphones jack and general purpose
I/O pins. The reliability of headphones interconnection is guaranteed by the quality
control personnel of the FPGA and headphones manufacturers. The microphones will
be connected to the FPGA’s general purpose I/O pins using jumper wires designed for
this application.
Health and Safety Issues
One goal of our project is produce a safety conscientious product that prevents
any potential injury. There are many electrical components in our system that can
become hot and may contain sharp edges or points. To avoid the risk of damage when
Adaptive Noise Cancellation System
P a g e | 23
falling on the product or accidentally touching a potentially dangerous surface, the
system will be enclosed in a hardened case.
Another safety concern would be having the device emit signals that are harmful
to the human ears. We have provided a requirement that no audible tones will be
produced that could potentially harm or produce discomfort to the user’s ears.
Economic Context
Many of the existing noise cancellation systems are expensive. We aim to
provide an economically system that a more general audience can afford. The product
will be an affordable home system that can be used to provide a quiet work environment
by cancelling out any of the noisy electronics running in a room or any other noise
sources. This system will also be very affordable to universities or schools to create
quiet work areas where students will be able to study without the distraction of outside
noise.
Intellectual Property
A preliminary patent search revealed several existing patents which are related
to the system designed in this project. These results are given below.
United States Patent 8,750,531 entitled “Active Noise Cancellation” covers digital
and analog systems, which generate a signal to counter-act a noise signal. The LMS
algorithm is mentioned as a possible part of the adaptive filter in the system. This
patent does not cover the use of the algorithm, but the described algorithm
implementation is very similar to the system described in this project. This patent would
likely block the transformation of this project into a marketable product.
United States Patent 8,411,872 entitled “Adaptive control unit with feedback
compensation” covers a wide range of adaptive filters. The LMS algorithm and its
variations are mentioned as possible control algorithms. A system with a feedback
microphone is also mentioned. This patent would also likely block this project team
from selling the system built in this project.
Adaptive Noise Cancellation System
P a g e | 24
Cost Estimates
Component
Description
Cost
Our Cost
Availability
Omnidirection
al Microphone
$3.23
$0.60
In stock from InvenSense.
http://store.invensense.com/Produ
ctDetail/INMP441ACEZInvenSense-Inc/485883&pid=1135
Part Number: INMP441ACEZ
Lead Time: 4-5 business days
Surface-mount $0.43
PCB
Capacitors
$0.43
In stock from DigiKey.
http://www.digikey.com/productdetail/en/0/1276-1506-1-ND
Part Number: 1276-1506-1-ND
Lead Time: 3 business days
Surface-mount $1.15
PCB Resistors
$1.15
In stock from DigiKey.
http://www.digikey.com/productdetail/en/0/MCS0402-100K-CFCTND
Part Number: MCS0402-100KCFCT-ND
Lead Time: 3 business days
Superlux
HD668B
Headphone
$43.82
$0.00
In stock from Amazon.
http://www.amazon.com/SuperluxHD668B-Dynamic-Semi-OpenHeadphones/dp/B003JOETX8
Part Number: NA
Lead Time: 3-5 business days
Adaptive Noise Cancellation System
Xilinx Virtex-5
XC5VLX110T
$2,199.00
or
$799.00
(Academic)
P a g e | 25
$0.00
In stock from Digilent.
http://www.digilentinc.com/Product
s/Detail.cfm?Prod=XUPV5&Nav1=
Products&Nav2=Programmable
Part Number: 6003-410-008P-KIT
Lead Time: 2-3 business days
Total Cost
$2,247.63
or
$847.63
$2.18
Adaptive Noise Cancellation System
P a g e | 26
Testing Strategy
Engineering
Requirement
C
C
C
C
C, D
N
N
Test Description
Unit Testing
The purpose of this test is to test the
Matlab version of the LMS algorithm.
Since the Matlab software has already
been verified, the algorithm will be
verified by code inspection by a team
member who did not write the Matlab
code.
The purpose of this test is to test the
Matlab version of the FIR filter. Since the
Matlab software has already been
verified, the filter will be verified by code
inspection by a team member who did
not write the Matlab code.
The purpose of this test is to test the HDL
description of the FIR filter using a VHDL
testbench. Stimulus and expected output
data can be generated by the Matlab
model.
The purpose of this test is to test the HDL
description of the LMS algorithm using a
VHDL testbench. Stimulus and expected
output data can be generated by the
Matlab model.
The purpose of this test is to test the
Audio Codec on the board. A sinusoid
will be generated and passed through the
Audio Codec to verify that it is
functioning as expected.
The purpose of this test is to test the I2S
protocol library using a VHDL testbench.
The testbench will act as a SLAVE to
ensure the communication protocol is
functioning properly.
The purpose of this test is to test the
microphones use of the I2S protocol.
This will be accomplished by applying a
2.82 MHz clock to SCK, applying a 44.1
KHz clock to WS, driving L/R high, and
driving CHIPEN to high. The clocks will be
generated by the FPGA. The output will
be monitored on an oscilloscope.
Expected Result
The Matlab code should
accurately model the
operations required by the
LMS algorithm.
The Matlab code should
accurately model the
operations required by the FIR
filter.
The output HDL description
matches the expected output.
The output HDL description
matches the expected output.
The sinusoid will be heard
through the plugged in
headset.
The I2S protocol functions as
expected.
The microphone is using the
I2S protocol as
expected.
Pass/Fail
Adaptive Noise Cancellation System
C
C
N
C, K
D
A
B
D
P a g e | 27
Integration Testing
The purpose of this test is to test the
The system as a whole
hierarchical MATLAB model. This will be
functions as expected.
accomplished through testing all the
modules of the system by driving the
input signal.
The purpose of this test is to test the
The output HDL description
integrated HDL description of the noise
matches the expected output.
cancellation module using a VHDL
testbench. Stimulus and expected output
can be generated by the Matlab model.
The purpose of this test is to test the
Audio detected by the
integration of the microphone and the
microphone is passed through
Audio Codec. The FPGA will be
the Audio Codec without
configured to send the audio data from
distortion.
the microphone directly to the Audio
Codec.
The purpose of this test is to ensure that
There has been a noticeable
the algorithm works on the FPGA. The
drop in volume.
adaptive noise system as a whole will be
connected and tested for noisy input
signals in the frequency range of 40 Hz to
80 Hz. At least 20 individuals will be
polled to determine if there is a
noticeable drop in volume.
Acceptance Testing
The purpose of this test is to test the
A clear audio signal is
successful output of a signal to the
produced by the headset.
headphones. The input signal will be sent
through the Audio Codec, through the 3.5
mm jack, and to the headset.
The purpose of this test is to test the
accessibility of the on/off switch. The
switch will be pressed to test it.
The purpose of this test is to review the
system documentation for completeness.
This includes comments in the MATLAB
code and the VHDL description.
The purpose of this test is to ensure the
3.5 mm headphone jack is accessible to
the user. Plug the headphones in to
ensure the 3.5 mm jack is accessible to
the user.
The system powers on/off as
expected.
The document is thorough.
The 3.5 mm jack is accessible
to the user.
Adaptive Noise Cancellation System
E
F
F
F
H
I, J
L
M
P a g e | 28
Review the necessary components and
ensure the total cost of the
system does not exceed $1000.
This test verifies that the system
dimensions are within the required
dimensions. The dimensions of the case
will be measured to ensure the system
will fit in the enclosure.
This test verifies the safety of the system.
The enclosure will be checked for sharp
edges or exposed wires.
The system cost does not
exceed $1000.
This test verifies that the system is
aesthetically pleasing to a majority of
potential users. At least 10 individuals
will be polled to gather feedback on the
aesthetics of the system.
The purpose of this test is to test that the
20 Hz sine wave and a 20 kHz sine wave
can be detected by the microphones and
monitored on an oscilloscope.
This test verifies that the system's total
energy usage is within the required
usage. A watt-meter will be used to
monitor the instantaneous power and
the total energy in kilowatt-hours over a
12 hour period.
This test verifies the noise range
countered by the system. The system will
be tested with frequencies in the band 40
Hz to 80 Hz, in increments of 5 Hz, to
ensure cancellation of the signals within 3
seconds. This will be measured using a
stopwatch.
This test verifies that the gain of the
system output is below the required
threshold. Sensors will be used to
measure an ambient noise and the
output signal for the frequency band of
20 Hz to 20 kHz. This will be used to
calculate the output dB of the system.
(The sensor type is still to be determined,
but we could possibly use a standard
computer microphone.)
At least 80% of the individuals
polled agree that the system is
aesthetically pleasing
compared to a board with no
enclosure.
The sine waves are
successfully viewed on the
oscilloscope.
The enclosure is no more than
two inches
larger than the FPGA on any
side.
The enclosed system has no
sharp edges or exposed wires.
The instantaneous power is
less than ten watts
and the total energy in
kilowatt-hours is less than 0.3
kilowatt-hours.
The system successfully
counters all tones in
the frequency band within the
3 second window.
The system produces output
signals that are
below 85 dB.
Adaptive Noise Cancellation System
C
This test verifies that the functional
algorithm counter frequencies in the
band 40 Hz to 80 Hz. This will be
accomplished by sending these
frequencies through our functional
MATLAB simulation and listening to the
output file.
P a g e | 29
There has been a noticeable
drop in volume.
Initial algorithm testing will be performed in MATLAB. MATLAB has the
necessary tools to build and test DSP algorithms quickly and comprehensively. Also,
due to current coursework, all members of the project team will have specialized
training in the implementation of FIR filters in MATLAB by the end of the first phase of
the project.
Initial MATLAB models will be used to ensure that the noise cancellation system
can successfully be implemented in a virtual environment. These initial models will
focus on simply modeling the necessary mathematical operations. If necessary, more
complex models can then be created, which more accurately model the FPGA
implementation of the algorithms. This model could be used to generate files containing
the expected output values of sub-modules given a generated input signal. These
simulation results may be helpful during the hardware implementation debugging
process.
The initial MATLAB model will be constructed in the first phase of the project.
Additional, more complex models will be built in support of the hardware development.
In general, algorithm modifications will be simulated in MATLAB before a hardware
implementation is attempted.
The algorithm will be written in VHDL and placed onto the board using Xilinx ISE
tools. The actual VHDL implementation of the algorithm will be tested pre-synthesis
and post-synthesis with ideal test benches using a set of carefully selected test cases.
This will be done upon completion of the VHDL code for the algorithm. Once this is in
place, a computer will be connected serially to the board to capture data at all the input
and output locations. A user readable interpretation of the data will be designed to
observe the original signal coming in, the error signal coming out, and the feedback
signal for each iteration. This strategy will ensure that any errors at any stage of the
process can be found. If the data coming in originally are not what is desired, it may be
a reflection of an incorrect use of I2S. If the signal output of the FPGA does not have
corrected weights reflected on the LMS algorithm, it will show an incorrect
implementation of the algorithm. Lastly, if the feedback signal appears to be incorrect, it
will again point to an issue with the I2S protocol. The signals will also be captured by
an oscilloscope to help monitor the analog response of the system.
Adaptive Noise Cancellation System
P a g e | 30
Risks
Algorithm
Although the general structure of the algorithms needed for this project is known,
the exact variation of the LMS algorithm which will be used is uncertain. This decision
cannot be made until the information found in the investigation of the FPGA risk has
been combined with the findings of this investigation. The LMS algorithm variation will
be selected based upon the strengths and weaknesses of the target FPGA.
Board
The testing strategies proposed for the interaction with the FPGA have not been
confirmed to provide useful feedback that will help to ensure the project is functioning
properly or for debugging purposes. This uncertainty will be handled during actual
project implementation. The board also uses fixed point arithmetic, which will lead to
small round off errors. Research has shown a potential fix to this issue by shifting the
data left and performing the operations and shifting back right the same amount after
the computations are finished [9]. The error should be small enough that it will not
affect the signal enough to be noticeable, but it is something to keep in mind.
Interface
The user interaction with the system could also provide some difficulty. The
object here initially is to make the interface very simple. The system should
automatically work for a desired frequency range without user configuration. As the
project grows, the user may interact with the system in such a way that the user will be
able to choose the correct environment for optimal conditions. This more complex
interface could pose more risk to the project. Therefore, this will be monitored and
noted in the later progressions of the project.
Adaptive Noise Cancellation System
P a g e | 31
Milestone Chart
Milestone
Due Date
Board Choice: Choosing the correct board.
Finished Project Proposal: Finishing the project
proposal documentation.
Board Functions: Learning all the functions of the
board needed for our system.
Hardware: Researching and acquiring necessary
hardware.
PCB Layout: Finishing and ordering the PCB
layout for the microphones.
Functional Algorithm Modeling: Modeling the
functional algorithm in MATLAB
Learn Audio Codec Functions: Determining how
to enable and interact with needed registers to
accept digital input and output sound through the
line output.
Surface Mounting: Contact EE faculty members
to arrange surface mounting for PCB.
Surface Mounting: Complete surface mounting for
PCB.
Generate Test Data: Use MATLAB to generate
potential test data for the HDL descriptions of the
LMS and FIR filters.
Determine DSP Slice Functionality: Learn if it will
be necessary to tell the FPGA to use the DSP
slices and how to do it.
Behavioral Microphone HDL Description: Finish
HDL description of the microphone.
FIR Filter HDL Description: Finish the HDL
description of the FIR filter.
LMS Module HDL Description: Finish the HDL
description of the LMS Module.
I2S HDL Description: Finish HDL description of
I2S protocol.
Audio Codec HDL Description: Finish HDL
description of Audio Codec.
Top Level ANC Module: Design the top level state
machine to control all the modules.
Testing PCB: Testing the PCB for desired
behavior and issues with soldering.
Audio Codec: Test Audio Codec with Sinusoid
1 May 2015
18 May 2015
Team Member
Responsible
Michael Loper
Michael Loper
18 May 2015
Michael Loper
18 May 2015
Irtaza Ahmed
27 Aug 2015
Irtaza Ahmed
8 Sep 2015
Michael Foster
18 Sep 2015
Michael Loper
22 Sep 2015
Irtaza Ahmed
29 Sep 2015
Irtaza Ahmed
29 Sep 2015
Michael Foster
3 Oct 2015
Michael Foster
3 Oct 2015
Michael Foster
3 Oct 2015
Michael Foster
3 Oct 2015
Michael Loper
3 Oct 2015
Michael Loper
3 Oct 2015
Michael Loper
3 Oct 2015
Irtaza Ahmed
6 Oct 2015
Irtaza Ahmed
10 Oct 2015
Michael Loper
Adaptive Noise Cancellation System
I2S Testing: Testing the I2S communication
between the board and microphones are working
properly.
Testing HDL Descriptions: Finish testing the HDL
descriptions using Testbenches.
Board Implementation: Getting the HDL
descriptions implemented on the board.
Board Testing: Testing the HDL descriptions on
the board.
System Testing: Testing the system as a whole.
Finalizing Poster Board and Documentation:
Ensuring all documentation for the project as a
whole is ready and checked over.
P a g e | 32
19 Oct 2015
Michael Loper
20 Oct 2015
Irtaza Ahmed
20 Oct 2015
Michael Foster
27 Oct 2015
Michael Foster
3 Nov 2015
1 Dec 2015
Michael Foster
Michael Loper
Adaptive Noise Cancellation System
P a g e | 33
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Adaptive Noise Cancellation System
P a g e | 34
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