Firmware development
for the AM Board
Virginia Greco
Marie Curie Fellow, CERN
FTK IAPP Project
EP Meeting, 5th April, 2016
AMB (Associative Memory Board)
 The AMBoard hosts 4 FPGA
chips (HIT, ROAD,
CONTROL, VME).
 4 LAMB’s (Little AMB) are
connected on each AMB.
LAMB2
LAMB0
8 Slinks
8 Slinks
 The HIT chip receives 12
serial buses from the AUX
board (hit information from
SCT and PIXEL layers).
 The ROAD chip receives
roads (coincidences
between hits and patterns)
from the 4 LAMB’s and
send them to the AUX card.
HIT
12 Slinks
4 Slinks
8 Slinks
LAMB3
4 Slinks
P3
LAMB1
ROAD
HIT FPGA: monitoring
 The GTP module deINIT_EV (from Control)
EE Freeze (to Control)
SYSTEM_CLOCK
EE Detect
Lost Sync
Module
CLOCK
FSM
RD_en
/EF_
50 MHz
Hold=HF
GTP
RX
Module
RX_GTP_CLOCK
36
INP
FIFO
Dual
Clock
Data=BCBC1c1c
& CharisK=F
idle
GTP_
aligned
SYSTEM_CLOCK
Wr_en
RD_en=!EF
OPC_
INIT
36
1
0
wr_
out_fifo
End_EV_int
GTP
TX
Module
EF
SPY BUFFERS
36
100 MHz
F
F
Init_ev
HIT_BUS
TX_GTP_CLOCK
36
1
RD_en
Parallelized
Data
IDLE
Wr_en Word
0
FIFO
VME
OUT
FIFO
A
Dual
Clock
Hit_inp_reg
Hit_inp
50 MHz
IDLE
Word
36
Tmode
Parallelized
Data
HIT_BUS
HIT-SCT
D
e
l
a
y
reset
serializes the input
bitstream coming from
the AUX  parallel data
bus (32bits)
 This parallel data bus is
stored in a dual clock FIFO
(1024 kwords deep).
 Two flags:
 Empty FIFO (EF)
 Half Full FIFO (when the
FIFO is 70% full) (HF)
HOLD signal to the AUX.
F
F
OUT
FIFO
B
Dual
Clock
F Wr_en
F
Parallelized
Data
GTP
TX
Module
EF
TX_GTP_CLOCK
RD_en=!EF
50 MHz
HIT_BUS
HIT FPGA: monitoring
 Counters for the input FIFO: EF-time, HF-time.
 24 registers (EF-time and HF-time) for each FIFO
 monitoring how much time the input FIFO is empty or
half full (percentage on total time: 1s, 60s)
 Implemented and tested  DONE
VME FPGA: Block Transfer Function
 The VME interface controls the vme write and read
protocols, as well as registers and memories of HIT, ROAD
and CONTROL.

A Block Transfer function is needed in order to speed up the write
and read processes.


Single access protocol: the cpu (sbc: single board computer) asks to
access the bus for writing or reading on a single address; the request is
processed by the vme and an aknowledge signal is sent back to the sbc.
Block transfer access protocol: the sbc makes a single request of access
to the bus for writing or reading, the vme interface receives only the
first address of a bank (64 address in our case); the address is increased
by the vme, an aknowledge signal is sent when each data is written; the
bus is released only when all the block of data has been processed
(written or read).
VME FPGA: Block Transfer Function
 For AUX board
 The vme interface increases the address and send the correct one to the
board, which is responsible for the write and read protocols.
 Implemented and tested  DONE
 To program the AM chips on the LAMB’s and to write the
pattern bank on the AM chips.
 The vme interface increases the address and manages all the control signals
necessary for writing and reading; it also feeds the data to the LAMB’s.
 Implemented; tests ongoing  Almost done
 To program the FPGA’s on the AM board (HIT, ROAD, CONTROL)
and to read the spy buffers of HIT and ROAD.
 Analogous to the protocol for the AM chips.
 Implemented  To be tested
What’s next
 Test and commissioning of the block transfer function for
LAMB’s and for AMB chips’ programming.
 Tests of the BT on AMBoards v4 and AM chips v6 at USA 1
(in the final system).

Up to the moment, all the tests have been done on the AMBoard v3
with AM chips v5 and v6 in LAB4.
 Cooling test at USA 15.