Scheduler for A
Memory
Interface Card
Gera Weiss
Weizmann Institute of Science
Input and Output buffers
Input buffer
One byte enters while four bytes
diffuse to the register.
Buffer
Register
Output buffer
One byte gets out while four bytes
diffuse from the register.
Buffer
Register
Without Loss Of Generality
Only Input Buffers
Green Flows out
Buffer
Yellow flows in
Buffer
Register
≈
Register
System Model
b<4  r<64
∆b=1
∆r=0
r<64  b<4
8 bit
16 bit
∆b=-3
∆r=4
∆b=-2
∆r=4
r<64  b≥4
r0, bb+3
3 time units
b≥4
r=64
b<4  r<64
∆b=1
∆r=0
∆b=2
∆r=0
r=64
r<64  b<4
r<64  b≥4
r0, bb+6
3 time units
b≥4
r=64
∆b=2
∆r=0
r=64
 r denotes the number of bytes in the register, b stands for the number of bytes in the
buffer.

Yellow transition represents usage of the bus which is a shared resource.

∆x = x(t+1)-x(t), where t is the discrete time.
Simulation
Time
Automaton
0
∆b=-3
∆r= 4
b<4
r< 64
r<64
∆b=1
∆r= 0
b≥4
r<64
r 0, b b+3
3 time units
b<4
∆b=1
∆r= 0
(b 22 - b 11)-3
16
State Space
r=64
r=64
48
r
b≥4
3
b 11
b 22
Buffer :
0
Register :
0
+ b 11
b
Score
Claim
Consider a sequence of n+1 register resets. Let b1 denote the number
of bytes in the buffer after the first reset and b2 the number of bytes
after the last reset. Then the time, T, passed between the first reset to
the last is T= (RegSize·n+b2-b1) / InBatch.
How many input bytes enter in one tick (2 or 1)
The number of bytes in the register (64)
Proof:
The difference in content of the buffer is b2-b1. In T time units the
buffer lost RegSize·n bytes to the DRAM and received T·InBatch bytes
as input. We get that b2-b1=T·InBatch-RegSize·n.
Corollary
In a valid schedule. Each eight bit buffer uses the bus
3/64 of the time and each sixteen bit buffer uses the
bus 3/32 of the time.
Proof:

Since the size of all buffers is finite, each buffer must reset
infinitely often. The number of bytes after resets must repeat.
b1
b2
b2
Reset duration · Number of resets

b1
b3
/
b4
b1
3n (RegSize / InBatch)n
b3
b2
b1
b1
Total time (by the claim in the preceding slide)
The claim is true between repetitions and therefore for all
the trace.
Conclusion
A necessary condition for schedulability is
(Tr/64)·(N8+2·N16) + Rt/ Rp ≤ 1
Where,




Tr is the time to reset a register (3 in our case).
N8 is the number of eight bit buffers.
N16 is the number of sixteen bit buffers.
Rt is memory refresh time and Rp is memory refresh period.
Schedule
If 2·Tr·N16 +Tr·N8 +Rt ≤ 64 and Rp ≥ 64 a schedule can be obtained
by lining resets along a time line of length 64 such that each eight bit
register resets once and each sixteen bit register resets twice.
Example:
0
Tr=3, N16 =4, N8 =5, Rt =10
3
16 bit
#1
32
16 bit
#1
6
16 bit
#2
35
9
16 bit
#3
38
16 bit
#2
12
16 bit
#4
41
16 bit
#3
15
8 bit
#1
44
16 bit
#4
18
8 bit
#2
8 bit
#3
21
8 bit
#4
24
27
32
8 bit
#5
64
Simulation
8 bit
16 bit
r
r
b
0
3
#1
6
#2
9
#3
12
#4
15
#1
18
#2
21
#3
#4
24
#5
27
b
32
#1
35
38
#2
41
#3
44
#4

The schedule works for every buffer size bigger than 3·InBatch.

This is the minimal buffer size because buffer content never drops
below InBatch and three slots are needed to absorb data during resets.

If Rp≥64 and Rt≤20 refreshes are possible.
64
A General Schedule
Rt
N16∙Tr
N8∙Tr
Refresh
DRAM
Reset all 16
bit registers.
Reset all 8
bit registers.
Max{0, 19-(N16+N8)∙Tr}
Wait until the first
register can reset again
N16∙Tr
Reset all 16
bit register.
Wait until the loop is
63 time units long.
Rt times

The first wait is needed because the minimal time between resets is 16
time units (the time to refill a register).

The length of this schedule is 64·Rt in which every 16 bit register
resets 2·Rt times and every 8 bit register resets Rt times. This means
that the schedule is periodic.

This schedule is possible under the necessary condition stated before
if the reset period is big enough to accommodate the loop.
More…

Continuous model.

Analysis of cards with other buffer parameters.

Resource sharing automata as a framework for
scheduling problems analysis.
Summary

An optimal schedule for the memory interface
card was presented.

A necessary condition for schedulability is
given.

The schedule can be adjusted to support other
card designs.

A model of resource sharing automata was
presented.