iVisual: An Intelligent Visual Sensor SoC with 2790fps
CMOS Image Sensor and 205GOPS/W Vision Processor
– Throughput:
• Traffic mismatch slows down
processors
– Power:
• parallel access of data memory
Parallel Memory
Access (2R1W/cycle)
XETAL-II (ISSCC’07)
RISC
• Video data revealed from
inter-chip traffic
Main Memory
– Privacy:
Parallel Data Buffer
• Challenges
SIMD Processor Array
•
Data
Video analysis technology Production: Data
430Gb/s
Consumption:
– Healthcare, HMI,
2.7Gb/s
surveillance, intelligent vehicle…
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iVisual Architecture
Light-in, answer-out SoC architecture, no
video data revealed to external
Avoid possible privacy problems
External Bus (AHB 2.0)
AHB Interface (2 Masters)
CMOS
Image
Sensor
(CIS)
Bitplane
Memory
Global
Processor
(GP)
Feature
Processor
(FP)
Decision
Processor
(DP)
Decision Feedback
Bitplane-based storage,
reduced data port
Additional memory
Reduce 43% process area
hierarchy between SIMD
array and memory
62% power reduction
iVisual Chip
Parallel-to-scalar
processor
36% throughput
2
increase
Throughput increase
Results
Cycle/Frame
: XETAL-II Architecture Model
131K
: iVisual
18K
12K
55K
8K
6K
2K
0.3K
Connected
Component
Extraction
Power efficiency
16-bin
Histogram
Image
Sub-Sample
Peak Power
Efficiency
(GOPS/W)
Peak Power 205
Efficiency
(GOPS/W)
50%
76.8
0.37
103
62%
39
107
0.6 x 4.5
51.2
3.25
16
iVisual
Elliptical
Matching
w/o FP
w/o PE cache
IMAP-CE [3]
205
40
Xetal-II [2]
iVisual
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