SHORT NOTES
697
It has been shown (independently) by Chow and Tannenbaum
that the n+1 characterizing parameters of a threshold function are
unique. Precisely (see [1]-[3]), and the next theorem follows.
Theorem: Let A1 be a threshold function and let A2 have the same
n+1 characterizing parameters as A1. Then A2= A1.
If we attempt to neglect the power parameter ir(A) in the above
theorem, the result is no longer valid. This can easily be seen in the
2-dimensional case by letting
A1
=
{ (1,
1) }
and A2 =
{(0, 0), (0, 1), (1, 0)}.
Then S(A1) =S(A2), but 7r(Al) 5'#sr(A2). Thus, by neglecting the
power parameter the example illustrates that the above theorem
becomes false in a strong sense, namely, there are distinct threshold
functions having the same characterizing vector S(A).
Despite the apparent loss of the uniqueness property, we show
that an interesting characterization of threshold functions arises by
neglecting the power parameter. In particular, we will show that
there are at most two threshold functions having a given characterizing vector. Further, if A1 and A2 are distinct threshold functions
having the same characterizing vector, then one of these functions
must have upper parity and the other must have lower parity. An illustration of this latter situation is furnished by the above example.
We consider an equivalence relation over the class of n-dimensional switching functions where two functions A1 and A2 are equivalent, denoted AlA2, if and only if their characterizing vetors are
identical, i.e., S(A1) = S(A2). The class of all 22' switching functions
is then naturally partitioned by this relation into equivalence classes,
called characterizing classes
e1, 02, * *X.
Thus, two switching functions are in the same characterizing class if
and only if they have the same characterizing vector.
If A is a function in Ci, then A is called a representative of Ci.
If A should possess the unique minimum cardinality (power) of any
member in the class Ci, i.e., if A, A1ECi and A#A1 implies 7r(A)
<r(Al), then A is called the minimum representative of its class.
Likewise, A is called a maximal representative of its class if A,
Al1Cj and A'19Ai implies 7r(A) > r(AL). It may be noted that there
is no a priori reason that a characterizing class has a minimal or
maximal representative.
Theorem: Let A be a threshold function. Then A is the minimal
(maximal) representative of its class if and only if it has upper
(lower) parity.
Proof: Let A and A1 be distinct functions in the same characterizing class and let ir(A) = M, X (A,) = N, and Xr (AnAA) =P. Then
for any weight vector w
E w-v
"EA
=
w-S(A)
=
w*S(Al)
=
vuA1
w.v.
(1)
By deleting the vertices common to A and A1
E
veA-A1
w.v= 2 W.V.
vEA1-A
(2)
If we now assume A to be a threshold function with threshold t
and weight vector w, it follows that for v eA-A1 (which implies
vEA) we have t<w- v by definition. Thus
(M - P)t < E W.V.
vEA-Al
(3)
Likewise, for vEA1-A (which implies vGEA) it follows that w'v<t,
hence
, w v < (N -P)1.
veA1-A
(4)
From (2), (3), and (4),
If we now assume the threshold function A to be a minimal representative of its class, then M< N, which together with (5) implies
t>O. Hence A has upper parity by the lemma above. Conversely, if
A has upper parity then t>O, and (5) yields M<N. The latter
merely says that A is the minimal representative.
Likewise, if we assume the threshold function A to be a maximal
representative, then M> N which implies t<0. Hence, by the lemma
A has lower parity. Conversely, if A has lower parity then by the lemma
t<0, whence M>N, i.e., A is the maximal representative of its class.
Corollary 1: If A is a threshold function, then it is either a minimal
or a maximal representative of its class.
Proof: A must be either of upper parity or of lower parity. The
result then follows from the theorem.
Corollary 2: There are at most two threshold functions having a
given characterizing vector S(A). Further, if there are exactly two
threshold functions with this characterizing vector, then one must
have upper parity and the other must have lower parity.
Proof: The class determined by S(A) has at most one maximal
and one minimal representative, by definition. Inasmuch as a threshold function must be either a maximal or minimal representative,
it follows that there are at most two such functions in any class.
Further, if there are exactly two threshold functions in a class, then
one must be a minimal representative, in which case it has upper
parity, and the other must be a maximal representative, in which
case it has lower partiy.
The above theorem together with its corollaries demonstrates
that if a switching function A is known to be a threshold function,
then the function is completely determined by its characterizing
vector together with a knowledge of whether A has upper or lower
parity. This fact leaves open certain interesting problems. In particular, if we are presented with the characterizing vector of a
threshold function, together with its parity (upper or lower), can one
algorithmically determine the power of the function, i.e., retrieve the
Chow label of the function? Also, is the property of being a maximal
or minimal class representative a necessary and sufficient condition
for a function to be linearly separable? The main theorem only shows
the necessity of this condition.
REFERENCES
[11 C. K. Chow, "On the characterization of threshold functions," Proc. AIEE 2nd
Ann.
Symp. on Switching Circuit Theory and Logical Design, pp. 34-38, September 1961.
12] M. Tannenbaum, "The establishment of a unique representation for a linearly
separable function," Lockheed Missiles and Space Co., Sunnyvale, Calif.,
Threshold Switching Techniques Note 20, pp. 1-5, October 1961.
[31 S. T. Hu, Threshold Logic. Berkeley, Calif.: University of California Press,
1965, pp. 52-54.
A Synthesis Technique for Binary Input-Binary
Output Synchronous Sequential Moore Machines
MONROE M. NEWBORN, MEMBER, IEEE
Abstract-A "synthesis technique" is presented for "realizing"
any arbitrary binary input-binary output "synchronous sequential
Moore machine" in the form of a network composed of identical
2-state "component machines." With slight modification the
synthesis technique presented can be used to realize any given
n-input-p-output synchronous sequential Moore machine in the
form of a network composed of identical 2-state component
machines.
Arden has shown that any synchronous sequential machine can
be realized with some delay d using a set of component machines
that are logically complete. Two results of this note are that for a
given n-input sequential machine, 1) only one component machine
is necessary for "logical completeness," and 2) using that com-
(M - P)t < (N-)t
or
Mt <N1 .
(5)
Manuscript received September 7, 1967; revised April 1, 1968.
The author was formerly with the Dept. of Elec. Engrg., Ohio State University,
Columbus, Ohio. He is now with the Dept. of Elec. Engrg., Columbia University,
New York, N. Y.
IEEE TRANSACTIONS ON COMPUTERS, JULY 1968
698
r-I
ponent machine, the given sequential machine can be realized with
delay d= 1. In the case of a binary input machine, each component
machine has an input-output relation y(t+1)=fi(t)x(t)+f2(t)x(t)
where f1(t) and f2(t) are outputs of other component machines, and
x(t) is the input to the sequential machine.
Index Terms-Component machines, decompostion, finite-state
automata, logical completeness, realization, sequential machines,
synchronous sequential Moore machines.
t'YI,
-t~~~~~~~~~~
II. DEVELOPMENT OF SYNTHESIs TECHNIQUE
A binary input-binary output synchronous sequential Moore
machine (BIBOMM) is a synchronous system with a binary input
alphabet X = { x, }, a binary output alphabet Z = {z, zt}, a finitestate set S= {sl, S2, * *, s, }, a Boolean equation relating the output z(t) to the states si(t), s2(t),
,Sn(t)
z(t)
=
-
alss(t) + a2S2(t) +
* *
+
as5(t), (1)
Z
x
12
3
1
2
3
1
0
3
3
1
1
(a)
00
()
0
[_
[3
!
[2,
2
1_,
. t
(b)
Fig. 2. (a) Flow table of BIBOMM1. (b) Circuit diagrams of BIBOMMI.
x =0, and the subset wk is the largest subset of states which is mapped
into wi when x= 1. The variable Yq corresponds to the largest subset
w5 for which z = 1 in all states of the subset.
Assume the AND-OR-DELAY (AOD) logic circuit shown in Fig. 1 is
the basic building block for a given BI:BOMM. A network consisting
of 2n such circuits, AODI, AOD2, * *, AOD2n, with the input-output
relation of each AODi corresponding to (4), can be shown to be a
realization of a specified BIBOMM. (It will be assumed in future
circuit drawings that x and x are inputs to all AOD logic circuits although these inputs will not be explicitly shown.)
Example 1: Consider the flow table for BIBOMM1 shown in Fig.
2 (a). The system of logical equations is presented below [(6)-(12) ]. A
circuit diagram is shown in Fig. 2 (b). Note that the "trivial" AOD
logic circuits representing the empty subset and the identity subset
have been omitted. For notational purposes, state variable yi which
corresponds to subset wi-= {i, sf2, *, s i} will be denoted [i1,
i2, * *, i.]. The system of equations is:
.
where
-
1i
0
if z = 1 in state si
if z = 0 in state si,
and a system of Boolean equations relating each state si at time t + 1
to the states si, S2, * *, s, and to the input x at time t, i.e.,
a
si(t + 1)
=
=
[bi1s1(t) + bi2s2(t) + * * * + bi.s.(t)]x(t) (2
+ [CilSl(t) + Ci2S2(t) +
' * *
+ CiS()]X(t),
[1]
[2]
41
0
(2)
if xZ causes a transition from state sj to state si
if x does not cause a transition from state sj to state si.
Each cij is correspondingly defined.
Consider the realization of a specified BIBOMM. Let the set of
2" subsets of states of set S be called W. Thus
W = {wI, W2,
, W2"}.
(3)
Define 2" state variables yi, Y2, * , y2" as follows. Let yi= I in
those states which are elements of subset wi; let yi=0 in the other
states. Then for a given BIBOMM, the system of logical equations
which define each yi and the output z(t) is
= Yj(t)x(t) + Yk (t)x(t),
i = 1, 2, * * * , 2"
(4)
Z(t) = yq(t),
(5)
where Yi, Yj, and Ye correspond, respectively, to wi, wj, and Wk. The
subset wj is the largest subset of states which is mapped into wi when
Yi(t + 1)
=
=
[4]Lt + [2, 3]x
[1]x + [O]x
[2, 3]x + [1 ]x
[1 ]x + [2, 3]x
[2, 3]x + [I]x
[3] =
[1, 2] =
[1, 3] =
[2, 3] = [I]xl
Z() = [1, 31,
where
=
yi
_________
______ _ J~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ I
3z
The realization of a given sequential machine by interconnecting a
finite number of 2-state component machines has been investigated by Kleene [1], Arden [2], Krohn and Rhodes [3], and Zeiger
[4]. Arden's work, in particular, is relevant to this note. In his paper,
he defined a set of component machines to be complete "if it is possible
to construct a machine that represents any definite event with
some delay from a finite number of copies of machines of the set.'
He then showed that any sequential machine can be realized with
delay d using a set of component machines that are logically complete. The object of this note is to show that for a given n-input sequential machine, 1) only one component machine is necessary for
logical completeness, and 2) using that component machine, the
given sequential machine can be realized with delay d = 1.
The synthesis technique is most easily described for a binary input-binary output sequential machine, and thus this author has
chosen to present his results for this case. With slight modification
the synthesis technique can be used to realize any given n-input-poutput sequential machine in the form of a network composed of
identical 2-state component machines.
-
(a)
(b)
Fig. 1. (a) An AND-OR-DELAY logic circuit. (b) Its abbreviated symbolic form.
I. INTRODUCTION
-
Yk-
A
+
[1]x
(6)
(7)
(8)
(9)
(10)
(11)
(12)
where [I] is the identity subset and [4 ] is the empty subset. An input
of the empty subset corresponds to a logic 0 input and an input of
the identity subset corresponds to a logic 1 input.
Examination of Fig. 2 (b) should lead to the following two observations.
1) Not all AOD circuits have outputs. This implies that not all
state variables enter, either explicitly or implicitly, into the expression
for the output z(t). The state variables that do not enter either
explicitly or implicitly into the expression for the output are unnecessary for the realization of the given BIBOMM. One can see in Fig.
2 (b) that [2], [3], and [1, 2] are such state variables.
2) If each AOD logic circuit had the complement of its output
also available (Fig. 3) as an input to the other circuits, half as many
circuits would be necessary. One AODC circuit could be used in place
of the two AOD circuits. This is shown in Fig. 4 with the complement
of [2, 3] replacing [1].
SHORT NOTES
699
In
y II
x
I,
IL
1
{
Yk-
A
Y
2
j
3
-
4
(
y
(a)
t
Z(t)
=
=
[2, -3]x
[2,3]±+ [I]x
+
[1, 3].
(13)
(14)
(15)
III. A GENERAL SYNTHESIS PROCEDURE
A general procedure for deriving the necessary system of equations used to realize a given BIBOMM with AODC circuits is as
follows. Choose state variable Yi1 to correspond to the largest subset
wi1 for which z= 1 in all states. Thus the first equation is z(t) = Ys,(t).
The remaining system of necessary equations follows at once.
Y'i(t + 1)
Yi,(t + 1)
0
3
1
0
1
(b)
Fig. 5.
The resulting equations are:
[1, 3]
1
3
It)
Fig. 4. An AODC circuit for BIBOMM,.
[2, 3] = [I]x
3
5
(a)
Fig. 3. (a) An AOD circuit with the complement of the output also available-an AODC circuit. (b) Its abbreviated symbolic form.
134. An Zir
x
2
55
(b)
z
x
4
5
Y,(t)OX(t)
=
Yi2(l)x(l) +
=
Yi4(t)x(t) + Y15(W)x(l)
(16)
Yig(t + 1) = Yi2q5(t)x() + Yi2+510()x(t);
where q is the smallest integer for which every state variable (excluding 4 and I) appearing on the right side of the first q equations also
appears (or its complement appears) on the left side. Rewrite the
equations in a final form, inserting complemented variables where
appropriate on the right side of the equations.
Example 2. Consider the flow table for BIBOMM2 shown in Fig.
5 (a). The initial and final system of equations is presented below
[(17-(30)]. The circuit is shown in Fig. 5 b). The initial system of
equation is:
z(t) = [1, 2, 5]
(17)
[1, 2, 5] = [2, 3, 5]x + [1, 4, 5]x
(18)
(19)
[2, 3, 5] = [2, 3, 4, 5]x + [1, 2, 3]x
[1, 4, 5] = [1, 2, 3, 5] + [4, 5]x
(20)
+ [1, 2, 3]x
[2, 3, 4, 5] = [I]T
(21)
+ [i]x
[1, 2, 3] = [4]x
(22)
=
[1, 2, 3, 5] [2, 3, 4, 5]x + [I]x.
(23)
(a) Flow table of BIBOMM2. (b) Circuit diagrams of BIBOMM2.
The final system of equations is:
z(t) = [1, 2, 5]
[1, 2, 5] = [2, 3, 5]xt + [1, 4, 5]x
[2, 3, 5] = [2, 3, 4, 5]g + [1, 2, 3]x
[1, 4, 5] = [1, 2, 3, 5]1 + [li,2, 3]x
+ [1, 2, 3]x
[2, 3, 4, 5] = [I]x
[1, 2, 3] = [1, 2, 3, 5]i + [I]x
[1, 2, 3, 5]
=
[2, 3, 4, 5] + [I]x.
(24)
(25)
(26)
(27)
(28)
(29)
(30)
IV. CONCLUSIONS
It has been illustrated that every BIBOMM can be realized using
at most 2'-1-1 identical AODC circuits. Each AODC circuit is a
2-state Moore machine. In many cases far fewer than 2a-1-1 circuits are necessary. For a specified n-input machine each component
machine would have the following input-output relationship:
Yi(t + 1) = Yo(t)mo(t) + yl(t)ml(t) + * * + Y2n(l)m2n(t)
where mi corresponds to the ith minterm of the input variables.
This synthesis technique seems to be applicable to integratedcircuit design techniques. There are several other related problems
that deserve consideration. One problem is the addition of identical
redundancy to each component machine; this would allow certain
error detection and correction capabilities. A second problem is the
interconnection of modules: to what extent can regularity be introduced into the interconnection of the identical component machines?
A third problem is that of extending this technique to the asynchronous case.
REFERENCES
[11 S. C. Kleene, "Representations of events in nerve nets and finite automata,' in
Automata Studies, As,n. Math. Studies, no. 34. Princeton, N. J.: Princeton
University Press, 1956, pp. 3-42.
12] Symp.
D. N. Arden,
"Delayed-logic and finite-state machines, " Proc. AJEE 2ud Aun.
on Switching Theory and Logical Design, pp. 131-151, September 1961.
K.
B.
Krohn
and
J. L. Rhodes, 'Algebraic theory of Machines," Proc. Symp. on
[3]
of Automata. Brooklyn, N.Y.: Polytechnic Press, 1963.
Mathematical
Theory
H.
P.
Zeigler, 'Loop-free synthesis of finite-state machine,' Ph.D. dissertation,
[41
M.I.T., Cambridge, Mass.