Digital Design: A Systems Approach
Lecture 13: Metastability and Synchronization Failure
(or When Good Flip-Flops go Bad)
(c) 2005-2012 W. J. Dally
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Readings
• L13: Chapters 27 & 28
• L14: Sequential Logic Review
(c) 2005-2012 W. J. Dally
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What happens when we violate setup and hold time constraints?
d
D
q
Q
clk
d
clk
ts
th
tdCQ
q
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Look at structure of CMOS latch
• Storage loop gets initialized with an ‘analog’ value
• Latch is a “time-to-voltage” converter
DV
clk
+2
clk
Data transition time
th
-ts
d
V1
clk
+
V2
DV
-2
-
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Storage loop has a metastable state between 0 and 1
V2
Stable point
Metastable point
V1
+
Stable point
V2
DV
-
V1
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Dynamics of DV
V2
Stable point
Metastable point
Stable point
V1
+
V2
DV
-
V1
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Dynamics of DV
DV
1
e-1
V1
+
V2
DV
1t
-
2t
t
-e-1
-1
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Metastability Demonstration Circuit
Voltage-Controlled Delay
Increasing VC increases delay
Part Vdd GND
4093 14 7
4007 14 7
4007 14 7
4011 14 7
4007 14 7
4007 14 7
1u
6
100K
100K
No
U1
U2
U3
U4
U5
U6
VC
RS FFs under test
14
Buffer
13
U3
11
1
U1
9
9
10
10
12
8
U4
10
2
U4
3
Q1
4
Q1N
8
5
9
6
U4
Relaxation Oscillator
U1
1
3
2
1u
6
1K
100K
13
100K
3.3n
14
10
U2
11
U1
12
14
12
13
13
13
11
10
11
12
U4
U5
11
9
12
6
9
8
7
10
11
14
12
13
U6
9
6
(c) 2005-2012 W. J. Dally
Q2
8
7
Q2N
Metastable state of FF1 – 4007 Nand RS Latch
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Over time the waveform fills in
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Metastable state of 4011 Nand RS Latch
What’s going on here?
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Over time this waveform fills in too
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Actual circuit of 4011 Nand RS Latch
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Initial state when both inputs are low
0
0
1
0
1
1
0
1
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When both inputs go high, it becomes a 6-stage ring oscillator
Oscillation is metastable
1
1
0
1
0
0
1
0
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Oscillation is metastable
0
1
0
1
0
0
1
0
0
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0
1
0
16
If delays are balanced, ring sequences through six states
repeatedly
0
1
0
0
1
0
1
1
0
1
1
0
1
0
0
1
0
0
1
0
1
1
0
1
0
0
1
0
0
1
0
1
1
0
1
1
(c) 2005-2012 W. J. Dally
A Brute-Force Synchronizer
A
FF1 AW FF2 AS
D
D
Q
Q
Clk
Clk
A
AW
AS
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What if AW is still in a metastable state when FF2 is clocked?
Clk
A
AW
AS
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Calculating Synchronization Failure
(The Big Picture)
P(failure) = P(enter metastable state) x P(still in state after tw)
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Probability of Entering a Metastable State
•
FF1 may enter the metastable state
if the input signal transitions during
the setup+hold window of the flip flop
•
Probability of a given transition
being in the setup+hold window
is the fraction of time that is
setup+hold window
Clk
t +t
PE = s h = fcy (t s + th )
t cy
ts+th
tcy
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Probability of Staying in the Metastable State
•
Still in metastable state if initial
voltage difference was too small to
be exponentially amplified during
wait time
æ - tw ö
÷÷
DVS = DVF expçç
è tS ø
æ - tw ö
÷÷
PS = expçç
è tS ø
•
Probability of starting with this
voltage is proportion of total
voltage range that is ‘too small’
DVF=1
DVS
tw
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Failure Probability and Error Rate
•
•
Each event can potentially fail.
Failure rate = event rate x failure
probability
æ -t ö
PF = PEPS = (t s + th )fcy expç w ÷
è t ø
æ -t ö
fF = fePF = (t s + th )fe fcy expç w ÷
è t ø
Clk
ts+th
DVF=1
tcy
DVS
tw
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Example
•
•
•
•
•
•
•
ts = th = tdCQ = t =100ps
tcy = 2ns
must sample a fE = 1MHz asynchronous signal
PE = (.1+.1)/2 = 0.1
PS = exp(-1.8/.1) = exp(-18) = 1.5 x 10-8
PF = PSPE = 1.5 x 10-9
fF = fEPF = 1.5 x 10-3
• 1 failure every 656 seconds ~ every 11 minutes
• This is not adequate. How do we improve it?
• How do we get failure rate to one every 10 years ~ 3 x 108s (fF < 3 x 10-9)
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Synchronizing multi-bit signals
counter
Consider a 4-bit counter running on clk1 you need the value of this
counter sampled by clk2. Will the following circuit work? (assume tw >> t)
clk1
cnt_w
cnt
D
Q
4
D
4
cnt_s
Q
4
clk2
This happens, for example, in a FIFO where the head and tail
pointers are in different clock domains.
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Multi-bit signals (2)
When synchronizing a multi-bit signal, each changing bit is independently
synchronized
Consider what happens on the 0111 to 1000 transition. All bits are
changing. Each can independently fall either way.
counter
How do you fix this?
clk1
cnt_w
cnt
D
Q
4
D
4
cnt_s
Q
4
clk2
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Warning: The Surgeon General has determined that
passing binary-coded and one-hot signals through a bruteforce synchronizer can be hazardous to your circuits.
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Solution:
Use a Gray code counter
For all but the MSB:
next_b[i] = (b[i-1] & !(|b[i-2:0])) ? !xor(b[n-1:i+1]) : b[i];
For the MSB:
next_b[i] = (|b[i-2:0]) ? b[i] : b[i-1] ;
Can we use this Gray code for the head and tail pointers of our FIFO?
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module GrayCount4(clk, rst, out) ;
input clk, rst ;
output [3:0] out ;
wire [3:0] out, next ;
DFF #(4) count(clk, next, out) ;
assign next[0]
assign next[1]
assign next[2]
assign next[3]
endmodule
=
=
=
=
!rst
!rst
!rst
!rst
&
&
&
&
!(out[1]^out[2]^out[3]) ;
(out[0] ? !(out[2]^out[3]) : out[1]) ;
((out[1] & !out[0]) ? !out[3] : out[2]) ;
(!(|out[1:0]) ? out[2] : out[3]) ;
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#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
xxxx
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
0000
0001
0011
0010
(c) 2005-2012 W. J. Dally
Metastability and Synchronization Failure Summary
•
•
•
Clocking a flip-flop during the “keepout” interval may leave the storage node in an
“illegal state”
Some “illegal states” are Metastable
Time to decay to a legal state depends on log of initial voltage
t = -t log(DV (0))
•
•
Probability of entering metastable state is probability of hitting “keepout” interval.
ts + th
PE =
tcy
Probability of staying in metastable state after time T is probability that initial voltage
was too small to decay in time T
æ -t ö
PS = expç W ÷
è t ø
•
•
Brute-force synchronizer – sample signal and wait for metastable states to decay.
Don’t use on multi-bit signals unless they are Gray coded
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