Workshop Topics - Outline
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Workshop 1 - Introduction
Workshop 2 - module instantiation
Workshop 3 - Lexical conventions
Workshop 4 - Value Logic System
Workshop 5 - Data types A
Workshop 6 - Data types B
Workshop 7 - Operators
Workshop 8 - Signed arithmetic
Workshop 9 - Behavioral modeling A
Workshop 10 - Behavioral modeling B
Workshop 11 - Behavioral modeling C
Workshop 12 - Data flow modeling
Workshop 13 - Coding Styles
1
Workshop 12 - Coding Styles
 Processor Stack
 FIFO
 Pipeline
 Finite State Machines
– Moore and Mealy
– State Diagram
– Coding styles
 Exercise 12
2
Processor Stack
 Processor Stack is a Last-In-First-Out (LIFO) Register Array.
Last value pushed on the stack is the first one popped off it.
 A Stack is controlled by a single, internal, Stack Pointer (SP)
Register, containing the current read/write location.
 SP content is used to push data into
stack_array[7]
specific Stack location as well as pop
inout
data from specific Stack location. data
 Stack has data I/O port, clock, reset,
push
push, pop control signals and error
pop
flag (read from empty or write to full). err
clk
nrst
3
stack_array[0]
Guidelines for Stack Coding
// Initialize stack array registers to zero using for loop or $readmeh
If (rst) begin sp = 0 ; full = 0 ; empty = 1 ; err = 0 ; dout = 0 ; end
else begin
// out of reset
if (push)
// write to stack
begin
if (empty) begin stack[sp] = din ; empty = 0 ; end
else if (full) err = 1 ; // no vacant place for write
else begin stack[sp] = din ; sp = sp + 1 ; end /* increment stack
if (sp==depth-1) full = 1 ;
pointer (sp) */
end
else if (pop)
// read from stack
begin
if (sp == 0 && empty = 0) begin dout = stack[sp] ; empty = 1; end
else if (sp == 0 && empty = 1) err = 1 ; // read from empty stack?
else if (sp != 0) sp = sp-1 ; // decrement stack pointer
if (full) full = 0;
end
end
assign dataIO = (pop)? Dout : 8’bZ ; // continuous assignment
4
Stack Simulation
5
FIFO Register File
 First-In-First-Out is more complicated than stack.
Like pipeline, it has 2 ends to be controlled.
 FIFO has distinct input and output and often used to
balance between 2 clock domains with different data rates.
 There are 2 main conventions in representing FIFO read
and write pointers: a. point to the next valid (reg) address.
b. point to the most currently used one.
 In this course, we shall adopt the former convention (a).
 The read pointer must point to valid next data to be read.
 The write pointer must point to the unused register into
which the next data will be written.
6
FIFO Schematics
fifo_array[7]
write
pointer
read and write
pointers are internal
read
pointer
data_in
data_out
write
read
clki
clko
nrst
fifo_array[0]
7
Guidelines for behavioral FIFO Coding
// Initialize all FIFO register file to zero reg[width-1:0] fifo[0:depth-1]
If (rst) begin wp=0;full=0;empty=1; end //wp points to 1st empty slot
assign dout = fifo[0] ;
// first stage of fifo is output
always@(posedge clk) begin
if (rd & ~wr) begin // shift-out (assumes: at least 1 valid value in fifo)
for (i = 1 ; i < wp ; i = i + 1) begin
// shift all valid entries
fifo[i-1] <= fifo[i] ; wp <= wp-1 ; full <= 0 ; end
if (wp==0) begin empty <= 1 ; else empty <= 0 ; end
end
If (~rd & wr) begin // shift-in (assumes: at least 1 entry free)
fifo[wp] <= din ; wp <= wp + 1 ; empty <= 0 ;
if (wp==depth) full <= 1 ; else full <= 0 ; end
If(rd & wr) begin //simult shift-in/shift-out. At least 1 valid entry
for (i = 1 ; i < wp ; i = i + 1) fifo[i-1] <= fifo [i] ; fifo[wp-1] <= din ; end
end
8
FIFO Simulation
9
Pipeline
 Pipelines, queues, and FIFOs are common logic structures
which are all related, in the sense that data moves from
one storage location to another synchronously, based on
a strobe signal, usually a clock.
in
stage1 s1out
stage2 s2out
stage3
always @(posedge clock)
begin
// use non-blocking assignments
out
<= pipe[3] ;
pipe[3] <= pipe[2] ;
pipe[2] <= pipe[1] ;
pipe[1] <= in ;
end
// assignments order is irrelevant
10
out
Pipe Stage as Separate Module
 It is common to make a single pipe stage module and use
it repetitively, as follows:
module pipeline(out, in, clock) ;
input clock, in ;
output wire out ;
wire s1out, s2out ;
pipestage s1(s1out, in, clock),
s2(s2out, s1out, clock),
s3(out, s2out, clock) ;
endmodule
module pipestage(out, in, clock) ;
input clock, in ;
output reg out ;
always @(posedge clock)
out <= in ;
endmodule
11
Combinational Logic in Pipeline
 It is more interesting if there is some combinational logic
associated with each pipe stage.
Suppose each stage has some logic represented by a
function f1, f2, f3 which is applied to the input.
in
f1
s1
f2
s2
f3
s3
module pipeline(out, in, clock) ;
input clock, in :
output out ;
wire s1out, s2out, s1in, s2in, s3in ;
assign s1in = f1(in), s2in = f2(s1out), s3in = f3(s2out) ;
pipelinestage s1(s1out, s1in, clock),
s2(s2out, s2in, clock),
s3(out, s3in, clock) ;
endmodule
12
out
Finite State Machines
13
Two types of Finite State Machines
combinational logic
sequential logic
combinational logic
Moore State Machine
combinational logic
sequential logic
Mealy State Machine
14
combinational logic
Moore and Mealy FSMs
 There are two common variations of state machines, Mealy
and Moore machines.
 Mealy machines produce outputs based on both current
state and inputs.
 Moore machines produce outputs based only on the
current state.
 Typically, the clock is used to change the state based on the
inputs which have been seen up to that point.
It is often convenient to think that all state machine
activities, are taking place on the clock edge:
o sample inputs
o compute next state
o compute outputs
o change state
o produce outputs
15
State Machine Guidelines
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Draw a state diagram.
Label the states.
Allocate state encoding.
Label the transition conditions.
Label the output values.
Use parameters for the state variables.
Use two procedures (one clocked for the state register
and one combinational for the next state logic and the
output decode logic).
Use a case statement in the combinational procedure.
Have a reset strategy (asynchronous or synchronous).
Use default assignments and then corner cases.
Keep state machine code separate from other code
(i.e. don’t mix other logic in with the state machine
clocked and combinational procedures).
16
Sequence Detector State Diagram
 Sequence detector implemented with Mealy FSM. Detect a
sequence of 1011 in serial input and overlapping sequences
So, if 1011011 come, sequence is repeated twice.
nrst
state
zero
state
five
out=0
in=1
out=1
in=1
in=0
// parametric states
parameter zero = 2’b00,
one = 2’b01, two = 2’b10,
five = 2’b11 ;
17
in=0
State
one
in=1
out=0
in=0
state
two
out=0
in=0
in=1
State Machine Coding
module sd_1011( clk, nrst, in, out) ;
input clk, nrst, in ;
output reg out ;
reg [1:0] state ;
always @(posedge clk or negedge nrst)
begin
// use non-blocking assignments
if(!nrst)
begin out <= 0 ; state <= 2'b00 ; end
else
begin
// Register FSM outputs are Glitch-Free
case({state,inp}) //combined state & inp -> smaller code.
3'b000: begin state <= 2'b00 ; out <= 0 ; end
3'b001: begin state <= 2'b01 ; out <= 0 ; end
3'b010: begin state <= 2'b10 ; out <= 0 ; end
3'b011: begin state <= 2'b01 ; out <= 0 ; end
3'b100: begin state <= 2'b00 ; out <= 0 ; end
3'b101: begin state <= 2'b11 ; out <= 0 ; end
3'b110: begin state <= 2'b10 ; out <= 0 ; end
3'b111: begin state <= 2'b01 ; out <= 1 ; end
endcase
end
end
endmodule
18
Sequence Detector Simulation
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