TIMING CLOSURE IN SYSTEM-ON-CHIP ERA
Sam Appleton, CEO
CONFIDENTIAL
Challenges in SDC Creation & Verification
It can get a bit messy
“IP”/block level timing
“SoC/Chip level” timing
• Making sure design is fully
constrained
• integrating IP
• Finding balance between
timing exceptions and risk
• Verification of timing
environment
• Ensuring Hierarchical
Consistency
• Debugging Macro-Scale
problems
• Size & Complexity
IP level timing closure
It’s a balancing act!
“Minimal SDC”
“Relaxed SDC”
• constrain all functional
paths for correctness
• static path/mode
exceptions added
• over all modes
• one SDC per design mode
• don’t use any exceptions
• structural/formal MCPs
and False Paths
• minimal case analysis
• minimal clock definitions
• conservative clock
groups
• Clock/Data exceptions
• Use clocks to break up
timing domains
The Balancing Act
Low-Risk
Hardest Timing, More
Power & Area
Higher Risk
Easiest Timing, Less
Power & Area
1. Find set of timing relaxations that help meet timing goals
2. Ignore all other “available” relaxations that don’t help
3. Allow for reuse of results from previous uses of IP
The Verification Problem
• “Timing domain” Verification
– Debugging clocks, case, modes,
conflicts
– Ensure STA treatment is correct
– Automating manual debug previously
done with STA
• Functional Verification
– For exceptions, functional coverage is
needed
– Simulation OR formal (or both)
– Critical problem in signoff of timing
environment
SoC Integration
New Level of Complexity and Scale
• Size/Scale
– 20-700M instances
– 200-3000 clocks
– 20-250 IP blocks
– 20-200k timing exceptions
– 2 or 3 levels of hierarchy
– 10000s of lines of scripting
– Usually GL netlist
SoC Integration Challenges
• Leverage IP timing SDCs
• Make sure SoC is consistent with IPs
• Add toplevel constraints, make sure
consistent with IPs
SoC/IP Consistency
• Clocks
• Case Analysis
• Exceptions
• Boundary Budget
• Critical for Hierarchical
Flows
• Heavy use of ETMs for TAT
at toplevel make this
more critical
• Multiple causes of silicon
failure
Future Directions
• Closing the gap between timing and functional
verification
– Big need to make sure the timing specification is
functionally verified
– SDCs are just like any other manually-created input
– Finding optimal exceptions to aid in timing closure
• SoC integration and analysis
– Bigger, more complex SoCs
– Big need for hierarchical analysis and consistency tools,
that can aid with promotion & demotion of SDCs