Skew Aware Polarity Assignment in Clock Tree
Po-Yuan Chen
Kuan-Hsien Ho
TingTing Hwang
Department of Computer Science
National Tsing Hua University
HsinChu, Taiwan 300
Email: [email protected]
Department of Computer Science
National Tsing Hua University
HsinChu, Taiwan 300
Email: [email protected]
Department of Computer Science
National Tsing Hua University
HsinChu, Taiwan 300
Email: [email protected]
ABSTRACT
In modern sequential VLSI designs, clock tree plays an important
role in synchronizing different components in a chip. To reduce
peak current and power/ground noises caused by clock network,
assigning different signal polarities to clock buffers is proposed in
previous work. Although peak current and power/ground noises are
minimized by signal polarities assignment, an assignment without
timing information may increase the clock skew significantly. As
a result, a timing-aware signal polarities assigning technique is
necessary. In this paper, we propose a novel signal polarities assigning
technique which can not only reduce peak current and power/ground
noises simultaneously but also render the clock skew in control.
The experimental result shows that the clock skew produced by our
algorithm is 94% of original clock skew in average while the clock
skews produced by three algorithms (Partition, MST, Matching) [5]
are 235%, 272%, and 283%, respectively. Moreover, our algorithm
is as efficient as the three algorithms of [5] in reducing peak current
and power/ground noises.
I. INTRODUCTION
In modern sequential VLSI design, clock tree plays an important
role in synchronizing different components in a chip. Clock tree is
composed of a tree of clock buffers. As the clock source switches
in each clock cycle, it propagates from the root of clock tree to
leaves. Since all clock buffers switch in each clock cycle, the clock
network produces unacceptable peak currents and power/ground
noises. A large current moving atoms on the power line, called
electromigration problem [1], may damage the circuit and shorten its
lifetime. Moreover, the circuit performance will be degraded when
power noises caused by clock tree network are large. For example,
in [2], it shows that 0.1V power noise will incur 79.8% inverter
delay variations when the nominal Vdd is 0.6V by Berkeley Predictive
Technology Model with 45nm technology [3].
To reduce peak current caused by clock tree network, Nieh et al.
proposed an opposite-phase approach in [4]. We assume that there is
a binary clock tree composed of clock buffers. As the clock source
switches from 0 to 1, it propagates through the clock tree and makes
all buffers switch from 0 to 1. Since all buffers switch from 0 to
1, the clock tree network will absorb current from power (Vdd ) net,
which results in huge peak current. To reduce peak current, Nieh et
al. modified the clock tree as shown in Figure 1 where an inverter
denoted in black color instead of a buffer is used in clock tree. By
this simple modification, the clock tree can be separated into two
subtrees: one is triggered by a clock buffer and the other by a clock
inverter. The clock buffers in the subtree trigged by the clock buffer
switch from 0 to 1 while the clock buffers in the other one switch
in an opposite direction. Please note that the flip-flops in the subtree
triggered by a clock inverter should be replaced by negative-edge
triggered ones. Since half of the clock buffers switch in the opposite
direction, the peak current can be easily reduced.
Although peak current is successfully reduced in [4], the
power/ground noises in a local area are not. Samanta et al. [5]
observed that power/ground noises are sensitive to the locations of
clock buffers. As a result, they proposed three algorithms: (1) partitioning, (2) 2-coloring on minimum spanning tree and (3) recursive
min-matching to replace half of the clock buffers by inverters taking
buffer locations into consideration. Figure 2 shows a possible result
produced by [5]. Methods proposed in [5] are indeed effective in
reducing power/ground noises. Unfortunately, since half of the clock
buffers in the clock tree are replaced by clock inverters and clock
skew is not taken into consideration, it may result in, in the worst
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
0
0
1
Fig. 1.
0
Opposite-phase clock tree in [4]
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
A
0
0
1
1
0
1
0
1
1
1
0
0
0
1
B
Fig. 2.
Opposite-phase clock tree in [5]
case, one path with all buffers and the other path with all inverters. For
example, in Figure 2, the path from root to A consists of all buffers
while the path from root to B all inverters. In this case, serious clock
skew occurs in node A and node B. Although buffer/wire sizing
technique [6], [7] can be applied to modify clock tree network, it
incurs extra area overhead. Moreover, clock skew will be hard to
recover when routing and area resources are critical. To solve both
power/ground noises and clock skew problems simultaneously, we
propose a new design flow which not only reduce peak current and
power/ground noises but also render the clock skew in control.
The organization of this paper is as follows. In Section II, motivational examples are presented. In Section III, the design flow
and algorithms are discussed. The experimental result is shown in
Section IV. Finally, the conclusions are made in Section V.
II. M OTIVATION
In the previous work, the transition of buffers in a clock tree is
assumed to switch at the same time instance. Therefore, peak current
is computed out of sum-total buffers. However, due to the transition
lags caused by the delay of buffers, such way of computation is inaccurate. To verify this observation, SPICE simulation on benchmark
circuit s38584 (in ISCAS89 benchmark set) is conducted using TSMC
0.13 cell library. The clock tree is synthesized, placed, and routed by
SOC Encounter. The simulation result is shown in Figure 3, where
horizontal axis and vertical axis represent timing steps and current
consumed, respectively. In Figure 3(a), the consumed current of clock
tree network is presented level by level while in Figure 3(b), the
summation of consumed current of clock tree is presented. Since each
intermediate branch of the clock tree drives more than one children,
1. Procedure Skew Minimizing Algorithm (leaves, target, B I )
2. begin
3.
If(B I = buf f er)
4.
global max = buf maxtarget ;
5.
else
6.
global max = inv maxtarget ;
7.
Checking Global Max(leaves);
8.
Assigning negative polarity to leafj whose buf maxj > global max;
9.
Counting Number of Negative Polarity Leaves (leaves);
10.
For(each leafj in the list, inv min list, in decreasing order)
11.
If(leafj is not in negative polarity and target 6= j )
12.
Assigning leafj to negative polarity;
13.
Counting Number of Negative Polarity Leaves (leaves);
14. end
(a)
(b)
Fig. 3.
Current variations in s38584 benchmark circuit
Fig. 4.
the consumed current grows as the clock signal propagates to deeper
level in the clock tree. From Figure 3(a) and (b), we observe that peak
current occurs when the clock signal propagates to the leaves of the
clock tree. Therefore, to accurately reduce peak current of a clock
tree, only the leaves of the clock tree are critical. Thus, we propose
that instead of half of total clock buffers, half of the clock buffers at
leaves are replaced by inverters to reduce peak current. By changing
only the clock phase at leaves, our method not only reduces peak
current but also render the clock skew in control because at most
one buffer is replaced by an inverter in each path.
III. D ESIGN F LOW AND A LGORITHMS
A. Design Flow
In our design flow, the input is a pre-layout clock netlist and the
timing information of n leaves. As shown in motivation, our objective
is to select n2 buffers at leaves and replace them by inverters so that
the clock skew, peak current, and power/ground noises are minimized
simultaneously. Our design flow is composed of two major steps. The
first step in our design flow is to assign the polarities of all leaves
in the clock tree so that the minimum clock skew is obtained. In
the second step, we classify the leaves into two categories. The first
one is sensitive to the clock skew and the other is not. Then, we
reassign polarities of unsensitive leaves according to their location
information so as to reduce power/ground noises.
B. Polarity Assignment for Minimizing Clock Skew
As shown in Section II, peak current is produced when the clock
signal propagates to the leaves of the clock tree. As a result, assigning
appropriate polarities of leaves are important. A straightforward
algorithm will enumerate all possible implementations and find the
best one. This straightforward enumeration will be infeasible because
for n leaves, O(2n ) time is required. In this subsection, we propose a
polarity assignment technique which not only efficiently reduces peak
current by assigning half of the leaves to negative-polarity (inverter)
but also produces the minimum clock skew in polynomial time.
Before we proceed the algorithm, we first define some notations.
Let a leaf buffer be denoted as leafi and k flip-flops, F Fj , for 1 ≤
j ≤ k, be driven by leafi . Then buf maxi and buf mini are
defined as
buf maxi = M AX1≤j≤k (arrival(F Fj ))
buf mini = M IN1≤j≤k (arrival(F Fj ))
where arrival(F Fj ) is the arrival time from source to flip-flop,
F Fj . Similarly, if a buffer is replaced by an inverter, inv maxi
and inv mini are defined as
inv maxi = M AX1≤j≤k (arrival(F Fj ))
inv mini = M IN1≤j≤k (arrival(F Fj ))
where arrival(F Fj ) is the arrival time from source to flip-flop, F Fj .
We further define global max and global min as
global max = M AXi∈leaves (buf /inv maxi )
(1)
global min = M INi∈leaves (buf /inv mini )
(2)
The Skew Minimizing Algorithm algorithm
TABLE I
E XAMPLES : leafi S AND THEIR CORRESPONDING TIMING INFORMATION
leaf1
leaf2
leaf3
leaf4
leaf5
leaf6
buf maxi
2.00
1.99
1.90
1.89
1.87
1.85
inv maxi
1.97
1.92
1.85
1.82
1.81
1.80
buf mini
1.82
1.89
1.79
1.79
1.86
1.70
inv mini
1.80
1.82
1.75
1.71
1.79
1.64
where buf /inv denotes that either buf maxi or inv maxi is
computed depending on the type, buffer or inverter, at leaves. Then,
the clock skew is defined as follows:
skew = global max − global min
(3)
By Equations (1, 2, 3), we know the clock skew is the maximum
difference among all pairs of clock signal arrival times of flip-flops.
Our first algorithm is developed, for a given leaftarget , to assign
polarities of all leaves so that global max = buf maxtarget or
global max = inv maxtarget . The smaller skew of two skews
produced by the two cases is selected as the best skew for leaftarget .
In the following, without loss of generality, we assume a leave implemented using inverter is faster than that implemented using buffer.
Please note that the algorithm can be easily modified when buffer is
faster than inverter. Initially, let buf max list denote a sorted list
of all leaves in decreasing order where leaves are implemented using
buffer and the key for sorting is buf maxi . Similarly, inv min list
denote a sorted list of all leaves in decreasing order where leaves are
implemented by inverters and the key for sorting is inv mini . We
will explain the algorithms when global max = buf maxtarget
in the follows. The same algorithm is applied when global max =
inv maxtarget . At beginning of the algorithm, we check whether it
is possible to have global max = buf maxtarget . For each leafj ,
we check if buf maxj > buf maxtarget . If it is, we assign leafj to
negative-polarity. If inv maxj is still larger than buf maxtarget , it
means buf maxtarget can not be global max and the algorithm
returns false and terminates. While checking is performed, each
leafj whose buf maxj > buf maxtarget is assigned to negativepolarity so that global max = buf maxtarget is satisfied. After
this step, we count the number of leaves that are replaced by
inverters. If the number of leaves in negative-polarity is more than
half of leaves, the algorithm returns false and terminates because
only half of the leaves can be implemented using inverters. If the
number of leaves in negative-polarity is equal to n2 , the algorithm
successfully find n2 leaves in negative polarity and returns true. If the
number of leaves in negative-polarity is less than n2 , the algorithm
continues. For each leafj in the list of inv min list in decreasing
order, if leafj is not assigned to negative-polarity, leafj is selected
and assigned negative-polarity. The assignment continues until n2
leaves are assigned negative-polarity. The details of the algorithm
are presented in Figure 4.
We give the following example to demonstrate our algorithm.
Suppose there are six leaves, denoted by leaf1 to leaf6 , in the circuit.
Their corresponding timing information is list in Table I. The first
column lists the names. The following columns show their corre-
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Sort buf max list;
Sort inv min list;
Procedure Optimal Clock Skew (leaves)
begin
for(each leafi in leaves)
Resetting all leaves to positive polarity;
Skew M inimizing Algorithm(leaves, i, buf f er);
Resetting all leaves to positive polarity;
Skew M inimizing Algorithm(leaves, i, inverter);
Recording the best result so far;
end
Fig. 5.
The Optimal Clock Skew algorithm
sponding buf maxi s, inv maxi s, buf mini s, and inv mini s. Let
the clock skew values be computed when global max = buf max2 .
That is, Skew M inimizing Algorithm algorithm is invoked with
target = 2 and B I=buf f er (type). The list of buf max list
is sorted as buf max1 , buf max2 , buf max3 , buf max4 ,
buf max5 , and buf max6 . Similarly, the inv min list is sorted
as inv min2 , inv min1 , inv min5 , inv min3 , inv min4 , and
inv min6 . At the beginning of the algorithm, we check whether
buf max2 = global max can be satisfied. Since there is only one
leaf, leaf1 , whose buf max1 > buf max2 , we check whether
inv max1 ≤ buf max2 . Since inv max1 ≤ buf max2 , leaf1
is assigned negative-polarity and global max = buf max2 is still
satisfied. After this assignment, we count the number of leaves that
are in negative-polarity. Since there is only one negative-polarity
leaf, we continue the assignment by inv min list one by one. The
first leaf in inv min list is inv min2 . We cannot assign leaf2 to
negative-polarity because global max is required to be buf max2 .
Then, we select the next leaf. Since leaf1 is already assigned to
negative-polarity, we select the third leaf, inv min5 , and assign
leaf5 to negative-polarity. Similarly, leaf3 is selected and assigned
negative-polarity. After this assignment, there are three leaves (half
of leaves) with negative-polarity. Skew M inimizing Algorithm
finishes and returns true. The global max remains to be buf max2
which is 1.99 and global min is equal to buf min6 which is 1.70.
Hence when gloabl max = buf max2 , the clock skew is 0.29.
In fact, the above greedy Skew M inimizing Algorithm can
produce an optimal (minimum) clock skew when global max is set
to buf maxtarget after assigning n2 leaves to negative-polarity. The
optimality is proved as follows:
Theorem 1: The Skew M inimizing Algorithm in Figure 4 can
produce the optimal (minimum) clock skew while global max is
equal to buf maxtarget after assigning n2 leaves to negative-polarity.
Proof: Omitted due to page limit.
We have proved that the Skew M inimizing Algorithm
can produce the optimal clock skews while global max is
equal to buf maxtarget . We further propose an optimal clock
skew algorithm for general case. The basic idea is to invoke
Skew M inimizing Algorithm n times for each leaf and for each
leaf, global max = buf max and global max = inv max are
computed in clock tree. The leafi that produces the smallest skew
is the optimal solution. The optimal clock skew algorithm is shown
in Figure 5.
The optimality of the Optimal Clock Skew is proved as follows:
Theorem 2: The Optimal Clock Skew algorithm in Figure 5 can
produce the optimal clock skew.
Proof: Omitted due to page limit.
Take
the
leaves
in
Table
I
as
an
example.
Skew M inimizing Algorithm(leaves, 1, buf f er)
returns
global max = 2, global min = 1.70, and clock skew is 0.3. Then,
Skew M inimizing Algorithm(leaves,1,inverter)
returns
global max = 1.97, global min = 1.70, and clock
skew is 0.27. Similarly, Skew M inimizing Algorithm(lea
ves,2,buf f er) returns global max = 1.99 (buf max2 ),
global min = 1.70, and clock skew is equal to 0.29.
Since
all
other
leaves
can
not
be
global max,
Skew M inimizing Algorithm will return false. Hence,
the optimal clock skew is 0.27 when leaf1 is invoked for
Skew M inimizing Algorithm with B I = inverter.
The time complexity of Optimal Clock Skew algorithm is
O(n2 ).
C. Power/Ground Noises Reduction Algorithm
In subsection III-B, the polarity-assignment algorithm for optimal
clock skew is proposed. In this subsection, we propose an algorithm
to take into consideration power/ground noises reduction. First, for a
clock tree implementation produced by our Optimal Clock Skew
algorithm, we classify all leaves into three categories:
• groupI : for any leafj in groupI , buf maxj > global max.
• groupII : for any leafj in groupII , inv minj < global min.
• groupIII : others.
Leaves of groupI must be implemented using inverter. If not (implemented using buffer), global max is increased and hence skew is
increased. Similarly, leaves of groupII must be implemented using
buffer. If not (implemented using inverter), global min in decreased
and hence skew is increased. On the other hand, leaves of groupIII
can be implemented using either inverter or buffer because in either
case, global max and global min are not affected. For instance,
three leaves, leaf1 , leaf2 , and leaf6 , in Table I must be assigned
particular polarities with global max = buf max2 and global min
= buf min6 , where leaf1 and leaf2 are assigned an inverter and a
buffer, respectively, to retain the value of global max and similarly,
leaf6 is assigned a buffer to retain the value of global min. The rest
of leaves can be assigned either buffer or inverter without affecting the
values of global max and global min. We can utilize this property
to minimize power/ground noises. In this subsection, we propose an
algorithm for power/ground noises reduction. It uses the leaves in
groupIII to minimize the power/ground noises.
First, we model the leaves as a graph G = (V, E) where |V | is
the collected set of all leaves. There are three types of edges, typea ,
typeb , and typec . They are defined as follows:
• typea : one end connecting a leaf that is implemented as a buffer,
and the other connecting a leaf with undetermined polarity.
• typeb : one end connecting a leaf that is implemented as an inverter,
and the other connecting a leaf with undetermined polarity.
• typec : both ends connecting leaves with undetermined polarity.
Since the power/ground noises are very sensitive to distance between
leaves, the weight of an edgei,j is assigned the distance between
leafi and leafj .
We propose Noise Reduction Algorithm to reduce power/ground
noises by assigning polarities to leaves in groupIII . At the beginning, leaves in groupI and groupII are assigned with appropriate
polarities described above to retain the same clock skew. Then, we
construct graph G(V, E) and assign type to each edge. Next, polarity
assignment to leaves of edges in groupIII starts. First, we check if
the number of buffers, |buf |, is larger than the number of inverters,
|inv|. If it is, an edge with the smallest weight is chosen from typea
and undetermined end is assigned to negative-polarity. Similarly, if
|inv| > |buf |, an edge with the smallest weight is chosen from
typeb and undetermined end is assigned to positive-polarity. These
two steps is to guarantee that the number of buffers and the number
of inverters are the same. Otherwise, we will have |buf | = |inv|.
In this case, an edge with the smallest weight is chosen. There are
three cases. Case 1 is that the chosen edge belongs to typec . We
mark the two ends with different signs, ’+’ and ’−’, and record it
as delay assignment group. The markings are only used to make
sure the two ends with different polarity. The actual assignment will
be performed when an edge of typea or typeb is selected and its
one end connects to this delay assignment group. Case 2 is that
the chosen edge is from typea . We assign the undetermined end to
negative polarity. Finally, case 3 is that an edge from typeb is chosen.
We assign the undermined end to positive polarity. In cases 2 and
3, if the undetermined end is marked with ’+’(’−’), the polarities
of all leaves in the delay assignment group will be determined
accordingly.
Figure 6 shows the steps when N oise Reduction Algorithm is
applied to the examples in Table I with global max = buf max2
and global min = buf min6 . At the first, leaf1 , leaf2 , and leaf6
are assigned appropriate polarities to retain the same clock skew as
shown in Figure 6(a). Since |buf | > |inv|, we choose edge2,3 from
typea and assign leaf3 to be an inverter as shown in Figure 6(b). In
Figure 6(c), edge4,5 is chosen. Since edge4,5 belongs to typec , leaf4
and leaf5 are marked and put into delay assignment group as
shown in Figure 6(d). Then, in Figure 6(e), edge2,4 is chosen. Since
leaf2 is a buffer and leaf4 is in the delay assingment group, we
Buffers
2
1
2
5
6
(a)
Buffers
2
5
6
1
2
3
6
Inverters
1
5
-
Buffers
1
5
-
6
s5378
s9234
s13207
s15850
s35932
s38417
s38584
avg
3
(d)
Inverters
+
4
2
Circuits
1
+
4
(c)
Buffers
5
(b)
Buffers
Inverters
4
4
Inverters
3
4
6
TABLE IV
C OMPARISONS OF GROUND NOISES BETWEEN OUR ALGORITHM AND
PREVIOUS WORK [5] IN mV
Buffers
Inverters
3
3
1
5
3
6
4
Example of N oise Reduction Algorithm algorithm
s5378
s9234
s13207
s15850
s35932
s38417
s38584
avg
Base
Skew
70.1
44.3
51.4
64.3
105.3
82.9
141.5
Partition
Skew
%
167
239
117
266
158
309
156
243
190
181
154
186
317
224
235
MST
Skew
174
136
160
192
272
217
300
Matching
Skew
%
164
235
129
292
221
431
166
259
340
324
207
250
271
192
283
%
249
309
313
299
259
263
212
272
Ours
Skew
64.2
45.9
49.3
61.2
92.4
75.5
129.4
%
92
104
96
95
88
91
91
94
assign leaf4 an inverter and leaf5 a buffer. The final result is shown
in Figure 6(f).
IV. E XPERIMENTAL R ESULTS
Experiments are conducted using ISCAS89 benchmark circuits
which are synthesized with T SM C 0.13µm cell library by Design
Compiler. All benchmark circuits are placed and routed by SOC
Encounter. The result of SPICE simulator is obtained by N anoSim
and 1.08V is used as supply voltage Vdd .
In each benchmark circuit, CLKBU F X8 (buffer) in T SM C
cell library is adopted to construct the clock tree. Furthermore, the
timing information is also computed for all leaves implemented by
CLKIN V X4 (inverter). To measure the resultant clock skew, the
maximum power/ground noises, and peak current, several sample
points are inserted into the SPICE file of each benchmark circuit.
We compare our experimental result to that in the previous work [5]
where three algorithms proposed are: partitioning (partition), 2coloring on minimum spanning tree (MST), and recursive minmatching (Matching). The results of clock skew in pico-second are
shown in Table II. The names of benchmark circuits are listed in
the first column. The column labeled, Base, lists the clock skew of
the original circuit. The second, third, and fourth columns are clock
skews produced by partitioning, 2-coloring on minimum spanning
tree and recursive min-matching algorithms, respectively. The last
column reports the result of our algorithm. Two values are reported
in each column. The first value represents the clock skew, and the
second one reports its normalization to the original clock skew in
percentage. The last row reports the average of the normalized values.
From the experiments, we can see that the resultant clock skew of
our algorithm is smaller than the original skew in most cases. The
algorithms in [5] produce large clock skew values (about 3 times of
the original clock skew in average).
TABLE III
C OMPARISONS OF POWER NOISES BETWEEN OUR ALGORITHM AND
PREVIOUS WORK [5] IN mV
Circuits
s5378
s9234
s13207
s15850
s35932
s38417
s38584
avg
Base
VDD
25.9
17.8
52.4
54.2
109.0
94.4
101.4
%
2.41
1.65
4.86
5.03
10.09
8.75
9.39
6.0
Partition
VDD
%
21.8
2.03
12.0
1.12
35.8
3.32
38.7
3.58
77.6
7.19
63.4
5.88
95.9
8.89
4.57
MST
GND
21.5
14.1
34.8
34.5
72.2
57.6
105.9
%
2.00
1.31
3.23
3.20
6.69
5.33
9.81
4.51
Matching
GND
%
22.3
2.07
14.1
1.31
34.4
3.19
34.5
3.20
68.6
6.35
81.9
7.59
73.0
6.77
4.35
Ours
GND
19.1
14.9
39.2
35.3
78.1
58.7
77.4
%
1.77
1.39
3.63
3.28
7.24
5.44
7.17
4.27
(f)
TABLE II
C OMPARISONS OF CLOCK SKEW BETWEEN OUR ALGORITHM AND
PREVIOUS WORK [5] IN PICO - SECOND
Circuits
Partition
GND
%
19.3
1.79
9.8
0.91
32.0
2.96
41.0
3.80
76.5
7.09
52.8
4.89
102.1
9.46
4.42
TABLE V
C OMPARISONS OF PEAK CURRENT BETWEEN OUR ALGORITHM AND
PREVIOUS WORK [5] IN mA
Circuits
Fig. 6.
%
2.23
1.66
5.06
4.02
8.27
8.24
11.1
5.8
Inverters
2
(e)
Base
GND
24.1
17.9
54.6
43.3
89.3
89.0
120.1
MST
VDD
17.5
14.7
34.6
31.9
80.7
62.7
75.5
%
1.62
1.37
3.21
2.96
7.48
5.81
6.99
4.21
Matching
VDD
%
19.3
1.79
13.2
1.23
31.4
2.92
41.6
3.86
80.8
7.48
70.0
6.49
81.9
7.59
4.48
Ours
VDD
22.3
14.6
51.9
46.3
82.9
66.2
76.9
%
2.07
1.36
4.81
4.29
7.68
6.13
7.13
4.78
s5378
s9234
s13207
s15850
s35932
s38417
s38584
avg
Base
Cur.
11.1
7.1
33.5
25.9
78.3
75.6
67.2
Partition
Cur.
%
7.3
66.3
5.0
71.2
19.4
57.9
18.8
72.6
55.2
70.5
47.4
62.8
50.8
75.6
68.1
MST
Cur.
7.03
5.1
21.8
15.4
54.2
43.6
43.1
%
63.0
72.6
65.1
59.6
69.2
57.7
64.1
64.5
Matching
Cur.
%
8.9
79.9
5.3
74.6
18.1
54.1
17.5
67.8
49.8
63.5
46.0
60.9
45.8
68.2
67.0
Ours
Cur.
6.7
4.9
20.7
17.5
57.3
48.2
50.1
%
60.8
68.6
61.8
67.6
73.1
63.8
74.6
67.2
In Tables III and IV, the maximum power/ground noises are
reported. The columns labeled VDD and % are maximum power
noises in mV and their normalization to Vdd in percentage. Similarly,
the columns labeled GND and % are the maximum ground noises and
their normalized value to Vdd , respectively. Tables III and IV shows
that the difference of power/ground noises between our algorithm and
algorithms of [5] is within 1%. In Table V, the result of peak current
is reported. It shows that the difference of peak current between our
algorithm and algorithms of [5] is within 3%. The experiments shows
that our algorithm is as efficient as algorithms in [5] in reducing peak
current and power/ground noises. More importantly, our algorithm
can effectively reduce the peak current and power/ground noise
without increasing clock skew.
V. C ONCLUSION
In this paper, we have proposed a novel signal polarities assigning technique which can not only reduce the peak current and
power/ground noises simultaneously but also render the clock skew in
control. The experimental result shows that the clock skew produced
by our algorithm is 94% of the original clock skew in average
while the clock skews produced by three algorithms (Partition, MST,
Matching) [5] are 235%, 272%, and 283%, respectively. Moreover,
our algorithm is as efficient as three algorithms of [5] in reducing
peak current and power/ground noises.
R EFERENCES
[1] John P. Uyemura, ”Introduction to VLSI Circuits and Systems,” JOHN
WILEY & SONS, INC.
[2] Sachin S. Sapatnekar, and Haihua Su, ”Analysis and Optimization of
Power Grids,” IEEE Design and Test Computers, vol. 20, issue 3, pp.
7-15, May-June 2003.
[3] Predictive Technology Model,
http://www-device.eecs.berkeley.edu/˜ptm
[4] Yow-Tyng Nieh, Shih-Hsu Huang, and Sheng-Yu Hsu, ”Minimizing Peak
Current via Opposite-Phase Clock Tree,” IEEE/ACM Design Automation
Conference, pp. 182-185, Jun. 2005.
[5] Rupak Samanta, Ganesh Venkataraman, and Jiang Hu, ”Clock Buffer Polarity Assignment for Power Noise Reduction,” IEEE/ACM International
Conference on Computer-Aided Design, pp. 558-562, Nov. 2006.
[6] Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil Khatri, Anand Rajaram, Patrick McGuinness, and Charles Alpert ”Practical
Techniques to Reduce Skew and Its Variations in Buffered Clock Networks,” IEEE/ACM International Conference on Computer-Aided Design,
pp. 591-595, Nov. 2005.
[7] Matthew R. Guthaus, Dennis Sylvester, and Richard B. Brown, ”Clock
Buffer and Wire Sizing Using Sequential Programming,” ACM/IEEE
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