CoPEC
ECEN 5807
Discrete-Time Modeling and
Compensator Design for
Digitally-Controlled
Switched-Mode Power Converters
ECEN5807
1
Converter System Analysis and Design
CoPEC
Component Design
iL(t)
+
+
–
Loop Gain Analysis
Iout
L
C
Vg
duty-cycle
d(t)
+
R
vo
_
_
1
Dead-time control
fs = 1 MHz
Digital
PWM
duty-cycle
command
Compensator
dc[n]
Gc(z)
ndpwm
error
e[n]
A/D
converter
error
ve
_
+
+
Vref
d[n]
ideal
DPWM
Power converter control-to-output
transfer function
Gvd(s)
Td (s ) = Gcd (e )e
Compensator
Gcd(esT)
sT
− st d
Gvd ( s )
vo(t)
1
sensing
gain
_
1
ideal
A/D
e-std
total
delay
Σ
ve[n]
+
vref (t)
• Analysis: introduction to discrete time systems,
mapping continuous-time designs into discrete
domain
• Design examples
• Discrete-time model and direct-digital design
ECEN5807
2
CoPEC
Buck Regulator with
Digital Voltage-Mode PWM Control
iL(t)
+
+
–
Iout
+
L
C
Vg
R
vo
_
_
Dead-time control
fs = 1 MHz
Digital
PWM
duty-cycle
command
Compensator
dc[n]
ndpwm
Gc(z)
error
e[n]
A/D
converter
error
ve
_
+
+
Vref
A digital feedback loop is created by adding data converters (output
voltage A/D and digital PWM) and a digital compensator
ECEN5807
3
Converter Modeling in Simulink
CoPEC
L
Q1
Top-level system model
RL
RC
Vg +
–
Q2
R
C
Constant input voltage
Switch network
Buck converter subsystem
Constant
duty-cycle
command
Simulink models are
well suited for
evaluation of digitallycontrolled SMPS
Pulse-width
modulator
subsystem
Load modeled as a resistor R, iout = Vo/R
ECEN5807
4
CoPEC
Digitally Controlled Buck Converter
Simulink Model
Digital PWM
A/D converter
• The buck converter
block is the same as
in the continuoustime system
• Note the parts of the
system that model
the digital controller
including:
– A/D converter
– Discrete-time
compensator, and
– Digital PWM
Discrete-time
compensator
ECEN5807
5
CoPEC
Start-Up and Step-Load Transient Waveforms
Digital Controller
Analog Controller
Vo
iL
• Example waveforms shown for digital and analog controllers
• Only slight differences associated with quantization and saturation
• Digital controller model includes A/D converter, discrete-time compensator and
digital PWM blocks
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6
CoPEC
Discrete-Time
System Modeling and
Compensator Design
Discrete-time emulation approach
• Re-use known (averaged) models and standard
analog compensator design techniques
• Map to discrete time
Direct approach
• Discrete-time converter model
• Direct-digital compensator design
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CoPEC
Benefits of Analog Design Approach
• Large and small-signal averaged models of all system
blocks are readily available and well understood
• Complete design performed in the frequency domain
• Design oriented analysis based on intuitive relationships
between frequency response and system specifications
• Extensive design experience and existing, proven designs
available
¾ Goal: tap the benefits above & extend to design of digital
controllers for switching converters
¾ First, compare continuous and discrete designs for a
simple integral compensator …
ECEN5807
8
Integral Compensator: Continuous
CoPEC
Simple integral or dominant pole
compensation used to achieve high dc gain
C
R
ve(t)
vc(t)
¾ Could assume a solution form and
solve for unknown coefficients to
derive output response
¾ Prefer to analyze the system transfer
function in the s-domain through
the Laplace Transform:
H int ( s ) =
Resulting time-domain differential
and integral equations describing
system behavior
τi
dvc (t )
= −ve (t )
dt
τ i ∫ dvc = − ∫ ve (t )dt
Vc ( s )
1
=−
Ve ( s )
sτ i
Resulting system pole/zero diagram and
frequency response, useful for intuitive,
design-oriented analysis
Im(s)
|H(jw)|
20dB/dec
Re(s)
0dB
log f
fo=1/2πτi
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CoPEC
Integral Compensator: Discrete-Time
¾ Let’s consider how to derive a
discrete-time equivalent to the
integral compensator
• First, sample the input error
signal with a sample period T:
ve(t)
T 2T 3T 4T
t
ve (t ) t =nT = ve (nT ) = ve [n]
• To derive an equation for the
discrete compensator output, we
need an approximation to the
continuous integral (or area
under the curve)
ECEN5807
• A zero-order-hold (ZOH) or
forward rectangular approximation
is shown, resulting in the output:
T
vc [n] = vc [n − 1] − ve [n − 1]
τi
• A more accurate straight-line
approximation (trapezoid) requires
the ability to compute the current
output based on the current input:
T
(ve [n] + ve [n − 1])
2τ i
¾ Again, from here, we can assume a
form of the discrete solution &
solve for the unknown coefficients
¾ We prefer to perform a (discrete)
transformation to simplify and aid
design and analysis
vc [n] = vc [n − 1] −
10
Discrete-Time Z-Transform
CoPEC
• The discrete-time equations can be written in “difference equation” and
infinite summation forms, as the dual to the continuous-time differential and
integral forms:
T
T n −1
∇vc [n] = vc [n] − vc [n − 1] = − ve [n − 1]
vc [n] = − ∑ ve [k ]
τi
τ i k = −∞
• We will use the terminology of difference equation, but continue to use the
recursive form due to the convenience in working with the z-transform and
hardware implementation
• The z-transform is a discrete-time, sampled-data dual of the Laplace
transform, which contains duals of all the well known intuitive characteristics
• Can be used to analyze constant coefficient, linear difference equations:
Z-Transform: Vc ( z ) =
Laplace
Transform:
∞
∑ v [ n]z
n = −∞
∞
c
Vc ( s ) = ∫ vc (t )e − st dt
−∞
ECEN5807
−n
Note that for z = esT the ztransform has the form of a
sampled version of the Laplace
Vc (e ) =
sT
∞
∑ v (nT )e
n = −∞
− snT
c
11
CoPEC
Mapping: s-plane to z-plane
• As noted, with z = esT the z-transform has the form of a sampled
version of the Laplace transform
• For complete mapping from the s-domain to z-domain, an
approximation to the integral is required
• Note that the s-plane stability boundary, s=jω, maps to the unit circle in
the z-plane (z = ejωT) Æ s-plane “left-half-plane (LHP)” will map to
considerations “inside the unit-circle” of the z-plane
ECEN5807
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CoPEC
Mapping examples: s-plane to z-plane
s-plane
s = σ + jω
z-plane
z = e sT = eσT e jωT = re jθ
Im(z)
jω
j
π
ω=
2T
σ
−j
π
2T
• Key observations:
s = 0 ( DC ) ⇒ z = 1
σ = 0 ⇒ z =1
σ → −∞ ⇒ z → 0
jω − axis ⇒ unit circle
ECEN5807
π
T
ω =0
Re(z)
ω=
2π
T
• Note: mapping from s Æ z is many-to-one
• This is due to periodic behavior around the
unit circle Æ leads to aliasing (more later)
• Multiple pole/zero in s Æ one location in z
• Multiple time signals have identical discrete
samples
13
CoPEC
Z-Transform for Integrator: ZOH
Zero-order hold, forward rectangular rule
T
Difference Equation:
vc [n] = vc [n − 1] −
Z-Transformation:
Vc ( z ) = z −1Vc ( z ) −
H int ( z ) =
Transfer Function:
T
ve[n]
τi
Linearity
Delay
τi
T
τi
ve [n − 1]
z −1Ve ( z )
Vc ( z )
T 1
=−
Ve ( z )
τ i z −1
_
Σ
z-1
vc[n]
+
ECEN5807
14
CoPEC
Z-Transform for Integrator: Trapezoid
Straight-line approx, trapezoid (bilinear or tustin) rule
Difference Equation:
vc [ n] = vc [ n − 1] −
T
(ve [n] + ve [n − 1])
2τ i
Z-Transformation:
Vc ( z ) = z −1Vc ( z ) −
T
(1 + z −1 )Ve ( z )
2τ i
H int ( z ) =
Transfer Function:
Vc ( z )
T z +1
=−
Ve ( z )
2τ i z − 1
_
ve [n]
Σ
T
2τ i
vc [n]
+
z-1
_
Σ
ECEN5807
+
15
CoPEC
Review Integral Compensator Example
Analog Design
ZOH discrete approx
C
T
R
ve(t)
vc(t)
dvc (t )
τi
= −ve (t )
dt
1
V (s)
H int ( s ) = c
=−
Ve ( s )
sτ i
τi
ve[n]
_
Σ
vc[n]
z-1
+
vc [n] = vc [ n − 1] −
H int ( z ) =
T
τi
ve [ n − 1]
Vc ( z )
T 1
=−
Ve ( z )
τ i z −1
Straight-line, trapezoid (bilinear) approx
T
(ve [n] + ve [n − 1]) ve [n]
vc [ n] = vc [n − 1] −
2τ i
T
V ( z)
T z +1
H int ( z ) = c
=−
Ve ( z )
2τ i z − 1
ECEN5807
_
Σ
vc [n]
+
2τ i
z-1
_
Σ
+
16
Integrator Freq Response Comparison
CoPEC
Frequency response
comparison
Color Code
analog (continuous)
ZOH, forward rect
bilinear, straight-line
ECEN5807
mag [db]
• Accurate results for
signal freq << 1/T
• Aliasing above 1/2T
• Clear difference in
phase errors between
discrete approx
-20
-40
-60
-80
3
10
4
10
5
10
100
phase [deg]
τ i = 1ms, T = 10 µs
0
50
0
-50
-100
3
10
4
10
frequency [Hz]
5
10
17
CoPEC
Mapping Approaches
• A number of different approaches are commonly used to
estimate the transformation from continuous to discrete
filter designs: three options are highlighted here
1. Bilinear Transformation (BLT)
– With the filter written in an integral time-domain
form, performs approximation to integral using the
area of a trapezoid between points
2. Pole-Zero Mapping
– Directly maps poles and zeros in the frequency
domain from s to z through the mapping: z = e sT
3. Triangle-Hold
– Performs a straight-line approx between samples of
the filter response, converts to z-domain
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18
CoPEC
Bilinear Transformation (BLT)
• Bilinear transformation (trapezoid integration or Tustin’s rule) with
pre-warping maps the entire left-half s-plane to inside the unit circle
• This correctly maps the stability axis (jω) to unit circle
1. Select a critical frequency (e.g. relative to sampling, filter corner or
system crossover frequency), ωcrit where frequency response of the
continuous and resulting discrete designs are to match
2. Substitute for s in H(s) to determine H(z):
H ( z ) = H (s) s =
ωcrit
z −1
tan (ωcritT 2 ) z +1
• Can be performed directly in Matlab using:
Matlab Code
% convert using BLT w/ prewarp at wx
Hdzp = c2d(Hczp,T,'prewarp',wx)
ECEN5807
19
Filter Mapping Example
CoPEC
• Consider a more complicated example with an additional pole
& zero:
Matlab Code

s 
1 + 
ωz 
ω
H (s) = z 
s 

1 + s 
 ω 
p 

f z = 1kHz
f p = 10kHz
T = 10 µs
fz = 1e3; % zero freq
fp = 10e3; % pole freq
Ts = 10e-6; % sampling period
% define continuous system
Hczp = zpk(-wz,[0 -wp],wp)
Hctf = tf(Hczp)
• Apply pre-warp to BLT method at, for example, the
logarithmic mean of fz and fp
• Resulting discrete-time filter
z − 0.9389)( z + 1) 0.2472 + 0.01411z −1 − 0.2321z −2
(
H ( z ) = 0.24721
=
1 − 1.521z −1 + 0.5207 z − 2
(z − 1)(z − 0.5207)
ECEN5807
20
Filter Example (T=10µs)
CoPEC
20
f p = 1kHz
f z = 10kHz
mag [db]
0
-20
Ts = 10 µs
-40
f s = 100kHz
2
10
3
4
10
10
5
10
phase [deg]
100
50
Color Code
0
continuous
bilinear
-50
-100
2
10
3
4
10
10
5
10
frequency [Hz]
ECEN5807
21
Filter Example (T=40µs)
CoPEC
20
f p = 1kHz
f z = 10kHz
mag [db]
0
Ts = 40 µs
-20
f s = 25kHz
-40
2
10
3
4
10
10
5
10
phase [deg]
100
Color Code
50
continuous
0
bilinear
-50
-100
2
10
3
4
10
10
5
10
frequency [Hz]
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Discrete Compensator Structures
CoPEC
• The procedure can now be generalized to higherorder compensator transfer functions, shown here
for a 3rd order system:
vc [n] = a1vc [n − 1] + a2 vc [n − 2] + a3vc [n − 3]
+ b0 ve [n] + b1ve [n − 1] + b2 ve [n − 2] + b3ve [n − 3]
Vc ( z ) bo + b1 z −1 + b2 z −2 + b3 z −3
H (z) =
=
Ve ( z ) 1 − a1 z −1 − a2 z −2 − a3 z −3
ve[n]
b0
+
Σ
vc[n]
+
z-1
b1
+
+
a1
+
a2
+
a3
Σ
+
z-1
b2
+
Σ
+
z-1
b3
Σ
+
• Many options for hardware implementation:
• Delays can be implemented as a code step (DSP/micro) or a clocked latch
(FPGA/custom)
• Multiply and add blocks can be implemented in arithmetic units,
dedicated multipliers, or look-up tables, which are especially useful when
a reduced set of possible inputs can be pre-computed
• Coefficients can be hardwired, boot-time programmable, or real-time
adaptive Æ with look-up tables, can also create non-linear control
ECEN5807
23
CoPEC
Additional Compensator Structures
k1
k3
k2
GC ( z ) = k1 +
+
z − 1 z − a1
k2
e[n]
+
Σ
+
+
-1
-1
Z
Z
k3
+
Σ
+
a1
+
Σ
d[n]
+
-1
Z
• Factor compensator into parallel form
• Can also cascade additional parallel structures
• All implement the same theoretical operation, but with different
hardware requirements and significantly different errors due to finite
word arithmetic
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CoPEC
Discrete Compensator Design Approach
1. Discrete-time emulation approach:
• Model the discrete components as
analog transfer functions
• Design a compensator based on
standard analog control techniques
including known delays from digital
approach
• Use a discrete equivalent map to
determine compensator coefficients
• Verify loop-gain with z=esT, then fine
tune coefficients for desired
performance
L
M
vout +
+
Vin
+
D
C
R
-
-
driver
H
Hvout(t)
DPWM
d[n]
Compensator
d[n]=f{d[n-1], d[n-2],..,e[n],e[n-1]..}
Digital Controller
A/D
e[n]
Hvout[n]
+
Vref[n]
¾ Next: consider the effects of A/D and D/A (DPWM) on loop
gain analysis
ECEN5807
25
A/D Modeling
CoPEC
Classical model of A/D operation
“hold”
operation
T
ve(t)
ve*(t)
hold
sampler
Sampling: impulse modulation
1 ∞
Ve* ( s ) = ∑ Ve ( s − jkω s ), ω s = 2π T
T k =−∞
|Ve*(jω)|
-fs
ECEN5807
-fs/2
0
fs/2
fs
f
quantizer
ve[n]
Aliasing
Must guarantee that all signal
frequencies of significant
magnitude that pass through the
A/D are band-limited below
1/2T = fs/2=Nyquist freq
26
CoPEC
Digital Control Delay Modeling
• In the combined A/D, computation and D/A loop delay from the
output sample to the duty cycle action is: td = td1 + DTs
vo(nT)
td
vo(t)
vgate(t)
(n-1)T
t
nT
sample
• The delay is included when analyzing the effective control-to-output
transfer function and loop gain in the s-domain when designing the
template compensator by adding an e-std term to the loop
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27
Small-Signal Model
CoPEC
duty-cycle
d(t)
Duty
1
Power converter control-to-output
transfer function
Gvd(s)
ideal
DPWM
vo(t)
Volts
sensing
gain
1
Volts
d[n]
Duty
Compensator Volts
Gcd(esT)
Volts
1
ideal
A/D
A/D and DPWM modeled as ideal (gain = 1)
Volts
e-std
total
delay
_
Σ
+
ve[n]
vref (t)
Total A/D sampling,
computation and
modulator delay
Loop gain: Td ( s ) = Gcd (e sT )e − std Gvd ( s )
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28
CoPEC
Practical Design Procedure
1. Design an analog compensator Gc(s) using traditional techniques
• Use an averaged model of the switching converter
• Model total expected delay with a single e-std block
• Include gain of output sensing
• Write a compensator template with matched number of poles and zeros
• If additional high frequency poles are needed to meet this constraint, select
desired location in z-domain (e.g. z = 0 for minimum hardware, z < 0
improved response), then add poles in s-domain to match the frequency
response between continuous and discrete models at a given frequency
(details given in example for BLT and a single HF pole)
• Design remaining comp parameters in s-domain to meet T(s) specs
2. Use BLT mapping with prewarp to derive digital compensator coefficients
3. Analyze the loop-gain using z = esT in the compensator and fine tune
coefficient values or compensator template & reiterate if needed
4. Select A/D & D/A (DPWM) resolution to achieve desired regulation,
compensator accuracy, and to avoid limit cycle behavior Æ verify & reiterate
ECEN5807
29
Design Example
CoPEC
Power stage parameters
iL(t)
+
+
–
Iout
+
L
C
Vg
R
vo
_
_
_
duty-cycle
command
PWM
Compensator
error
+
+
Vref
Point-of-Load Synchronous Buck Regulator
ECEN5807
• Vref = 1.8 V
• Iout = 0 to 5 A
Dead-time control
fs = 1 MHz
• Switching frequency:
fs = 1MHz
• Vg = 5 V
• L = 1 µH
• RL = 25 mΩ
• C = 200 µF
• Resr = 0.8 mΩ
30
CoPEC
Averaged Discrete Small-Signal Model
Loop gain
Td ( s ) = Gcd (e sT )e − std Gvd ( s )
duty-cycle
d(t)
1
Power converter control-to-output
transfer function
Gvd(s)
ideal
DPWM
vo(t)
sensing
gain
d[n]
Compensator
Gcd(esT)
1
_
1
ideal
A/D
e-std
total
delay
Σ
ve[n]
+
vref (t)
Initial design neglects quantization in A/D, DPWM and compensator
ECEN5807
31
CoPEC
Buck Averaged Small-Signal Model
Vg d
RL
L
iL
Gvd ( s ) =
+
Resr
vg +
–
D iL
+
–
R
D vg
C
Io d
f esr =
Qloss
1
= 1 MHz
2πCResr
L/C
=
= 2.36 → 7.4 dB
Resr + RL
Q = Qloss || Qload =
ECEN5807
fo =
1
2π CL
vˆo
dˆ
v
–
1+
Gvd ( s ) = Vg
s
ωesr
1 s  s 
+ 
1+
Q ωo  ωo 
2
= 11 kHz
Qload =
R
>5
L/C
QlossQload
< 2.36 → 7.4 dB
Qloss + Qload
32
CoPEC
Control-to-Output Frequency Response
50
Magnitude [dB]
0
Gvd(jω)
Phase [deg]
-50
-100
-150
-200
3
10
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4
10
5
10
33
Uncompensated Loop Gain with Delays
CoPEC
Tu ( s ) = e − std Gvd ( s )
Ts = 1µs
50
Magnitude [dB]
• Recall td models delay
from sample point to
falling edge of PWM
• Next, select and design
analog compensator
template
0
Phase [deg]
-50
-100
-150
td = 0
td = 200ns
td = 360ns
td = 1µs
-200
-250
-300
2
10
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3
10
4
10
frequency [Hz]
5
10
6
10
34
CoPEC
Design Examples
• Look at three design examples:
• Design #1
– td = 1.36µs (one cycle plus modulator delay)
– Conservative design
• Design #2
– td = 0.36µs (modulator delay only)
– Moderately conservative design
• Design #3
– td = 0.36µs
– Try to push the limits …
ECEN5807
35
CoPEC
PID Compensator Template
• Continuous-time (analog) template for discrete-compensator design can
be constructed using the same standard techniques, except:
• Zeros do not have to be real; complex zeros can be implemented
• Match number of poles & zeros; high frequency poles should be
added according to desired placement in z-domain and to match
frequency response between continuous template and resulting
discrete design at a critical frequency (depends on mapping used)
• Select a PID style template, including the required high frequency pole:
vc ωk 
s 
s  1




1+
1+
Gct ( s ) = =



vo
s  ω z1  ω z 2  1 + s
ωhf
• Prior to designing key parameters, fz1, fz1 and ωk, we need to select fhf
• Using BLT mapping with prewarp, the choice of fhf depends on:
• Placement of the z-domain pole, zp = a
• Frequency fcrit where the continuous and discrete-time responses
match exactly
ECEN5807
36
CoPEC
BLT Mapping, HF Pole Placement
• Two decisions are required:
• Selection of critical frequency, fcrit, for pre-warping (match
cont & discrete)
• Placement of high frequency pole, fhf
• Recommendation (starting point):
f crit = 0.1⋅ f s
• Set both frequencies relative to fs
f hf = 0.3078 ⋅ f s (a = 0)
• Place z-domain pole at zp = a:
f hf = 0.4617 ⋅ f s (a = −0.2)
• a = 0 for minimum hardware
• a = −0.2 (or less) for increased phase and gain at high
frequency (improve PM, degrade GM)
• In general, the required fhf for a desired fcrit and a is given by
f hf =
ECEN5807
f crit
1− a
tan (π ⋅ f crit f s ) 1 + a
37
Design #1: Compensator Design
CoPEC
• Place the real zeros below the power stage fo; try to maximize
loop gain at fo
• Place added z-domain pole at z < 0 for slight PM and GM
improvement
• Place target cross-over frequency at ~ 50 kHz (from Tu plot)
vc ω k 
s 
s  1




1+
1+
Gct ( s ) = =



vo
s  ω z1  ω z 2  1 + s
ωhf
Continuous-time PID
compensator template
f z1 = 0.7 f o
f z 2 = 0.9 f o
f crit = f s / 20
f cross = f s / 20
BLT
Gcd 1 ( z ) = 17.045 +
0.0368 22.0102
−
(z − 1) z + 0.4
a = −0.4
ECEN5807
38
Design #1: Loop Gain Response
CoPEC
Template (black), Discrete (blue) and Discrete Rounded (red) Loop Gain
td = 1.36µs
80
magnitude [db]
60
40
20
0
Template Design
-20
-40
3
10
4
10
5
10
6
10
Discrete Design
0
Results
fc = 50 kHz
PM = 49 deg
GM = 10.4 dB
phase [deg]
-50
-100
-150
-200
-250
3
10
ECEN5807
4
10
frequency [Hz]
5
10
6
10
39
Simulink Model
CoPEC
Closed-loop digitally-controlled synchronous buck switching converter model
CoPEC 2005
Vg
5
1
Out3
3
Input voltage
Out1
Vg
d
dc1
Quantizer
DPWM
limits
c
Vo
Vo
d
c
iL
iout
PWM
iout
iL
buck converter
Scope
Out2
2
Vo/R
Step load
.36
Krnd
Vo
R
Scope1
1
R
Gain
Load resistor
Gain1
dc
R1rnd
eq
eh
ed
e
z-1
Discrete
Transfer Fcn
A/D
Limits
Quantizer1
Zero-Order
Hold
Delay
td1
1.8
Constant
Vref
R2rnd
z-Prnd
Discrete
Transfer Fcn1
ECEN5807
40
CoPEC
Design #1: Load Transient w/out Quantization
1.85
td = 1.36µs
Vo
1.8
1.75
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
• Load transient:
2.5 A to 5 A
6.8
-4
x 10
8
6
iL
1.8
1.8
4
1.79
1.79
2
1.78
1.78
0
1.77
1.77
4.8
5
5.2
5.4
5.6
5.8
6
1.76
1.76
0.8
Vo
6.2
6.4
6.6
6.8
-4
4.8
4.8
4.85
4.85
x 10
4.9
4.9
4.95
4.95
55
5.05
5.05
5.1
5.1
5.15
5.15
5.2
5.2
-4
-4
0.6
d
xx 10
10
88
0.4
0.2
0
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
6.8
-4
x 10
ECEN5807
41
CoPEC
Design #1: Load Transient with Quantization
1.85
td = 1.36µs
Vo
1.8
1.75
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
6.8
-4
x 10
8
6
iL
Results
Stop osc inside LSB: 100 µs
Settle to within LSB: 20 µs
Transient peak: 40 mV
4
2
0
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
6.8
-4
x 10
0.8
0.6
d
0.4
0.2
0
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
• A/D quantization: 5 mV
• DPWM: 12 bits
• Load transient:
2.5 A to 5 A
6.8
-4
x 10
ECEN5807
42
CoPEC
Design Examples
• Look at three design examples: Settle to within LSB: 20 µs
Transient peak: 40 mV
• Design #1
– td = 1.36µs (one cycle plus modulator delay)
– Conservative design
• Design #2
– td = 0.36µs (modulator delay only)
– Moderately conservative design
• Design #3
– td = 0.36µs
– Try to push the limits …
ECEN5807
43
Design #2: Compensator Design
CoPEC
• Place the real zeros below the power stage fo; try to maximize
loop gain at fo
• Place target cross-over frequency at ~ 100 kHz (conservative)
• Place added z-domain pole at z = 0 for to avoid GM degradation
and simplify hardware
f z1 = 0.7 f o
f z 2 = 0.9 f o
f crit = f s / 10
f cross = f s / 10
BLT
Gcd 1 ( z ) = 26.3962 +
0.0839 23.4806
−
(z − 1)
z
a=0
ECEN5807
44
Design #2: Loop Gain Response
CoPEC
Template (black), Discrete (blue) and Discrete Rounded (red) Loop Gain
80
td = 0.36µs
magnitude [db]
60
40
20
0
Template Design
-20
-40
3
10
4
10
5
10
6
10
Discrete Design
0
Results
fc = 100 kHz
PM = 56.9 deg
GM = 12.3 dB
phase [deg]
-50
-100
-150
-200
-250
3
10
ECEN5807
4
10
frequency [Hz]
5
10
6
10
45
CoPEC
Design #2: Load Transient w/out Quantization
1.85
td = 0.36µs
Vo
1.8
1.75
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
• Load transient:
2.5 A to 5 A
6.8
-4
x 10
8
1.8
1.8
6
iL
1.79
1.79
4
1.78
1.78
2
1.77
1.77
0
Vo
1.76
1.76
4.8
5
5.2
5.4
5.6
5.8
6
6.2 4.86.4 4.85
6.6
4.8
4.85
6.8
4.9
4.9
-4
x 10
0.8
88
4.95
4.95
55
5.05
5.05
5.1
5.1
5.15
5.15
5.2
5.2
-4
-4
xx 10
10
0.6
d
0.4
0.2
0
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
6.8
-4
x 10
ECEN5807
46
CoPEC
Design #2: Load Transient with Quantization
1.85
Vo
1.8
1.75
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
6.8
-4
x 10
8
6
iL
Results
Stop osc inside LSB : 95 µs
Settle to within LSB: 15 µs
Transient peak: 22.8 mV
4
2
0
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
6.8
-4
x 10
0.8
0.6
d
0.4
0.2
0
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
• A/D quantization: 5 mV
• DPWM: 12 bits
• Load transient:
2.5 A to 5 A
6.8
-4
x 10
ECEN5807
47
CoPEC
Design Examples
• Look at three design examples: Settle to within LSB: 20 µs
Transient peak: 40 mV
• Design #1
– td = 1.36µs (one cycle plus modulator delay)
– Conservative design
Settle to within LSB: 15 µs
• Design #2
Transient peak: 22.8 mV
– td = 0.36µs (modulator delay only)
– Moderately conservative design
• Design #3
– td = 0.36µs
– Try to push the limits …
ECEN5807
48
Design #3: Compensator Design
CoPEC
• Place the real zeros around the power stage fo; try to maximize
loop gain at fo
• Place target cross-over frequency at ~ 200 kHz (fs/5)
• Place added z-domain pole at z = −0.4 (improve phase margin,
ignore GM degradation)
f z1 = 0 . 9 f o
f z 2 = 1.2 f o
f crit = f s / 7
f cross = f s / 5
BLT
Gcd 1 ( z ) = 71.6568 +
0.2707 90.1175
−
(z − 1) z + 0.4
a = −0.4
ECEN5807
49
Design #3: Loop Gain Response
CoPEC
Template (black), Discrete (blue) and Discrete Rounded (red) Loop Gain
80
td = 0.36µs
magnitude [db]
60
40
20
0
Template Design
-20
-40
3
10
4
10
5
10
6
10
0
Results
fc = 220 kHz
PM = 50.4 deg
GM = 2.6 dB
-50
phase [deg]
Discrete Design
-100
-150
-200
-250
3
10
ECEN5807
4
10
frequency [Hz]
5
10
6
10
50
CoPEC
Design #3: Load Transient w/out Quantization
1.85
td = 0.36µs
Vo
1.8
1.75
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
• Load transient:
2.5 A to 5 A
6.8
-4
x 10
8
1.8
1.8
6
1.79
1.79
iL
4
2
0
Vo
1.78
1.78
1.77
1.77
4.8
5
5.2
5.4
5.6
5.8
1.76
1.76
6
6.2
6.4
4.8
4.8
6.8
-4
4.85
4.85 x 4.9
4.9
10
0.8
4.95
4.95
55
5.05
5.05
5.1
5.1
5.15
5.15
5.2
5.2
-4
-4
xx 10
10
88
0.6
d
6.6
0.4
0.2
0
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
6.8
-4
x 10
ECEN5807
51
CoPEC
Design #3: Load Transient with Quantization
1.85
Vo
1.8
1.75
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
6.8
-4
x 10
8
6
iL
Results
Stop osc inside LSB : ∞
Settle to within LSB: 10 µs
Transient peak: 24 mV
Quantization effects!
4
2
0
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
6.8
-4
x 10
0.8
0.6
d
0.4
Note: DPWM has resolution
at output: Vg
0.2
0
• A/D quantization: 5 mV
• DPWM: 12 bits
• Load transient:
2.5 A to 5 A
12
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
2
6.8
= 1.2 mV
-4
ECEN5807
x 10
52
CoPEC
Design Example Summary
• Look at three design examples:
Settle to within LSB: 20 µs
Transient peak: 40 mV
• Design #1
– td = 1.36µs (one cycle plus modulator delay)
– Conservative design, fc = 50 kHz
Settle to within LSB: 15 µs
• Design #2
Transient peak: 23 mV
– td = 0.36µs (modulator delay only)
– Moderately conservative design, fc = 100 kHz
Settle to within LSB: 10 µs
• Design #3
Transient peak: 24 mV
– td = 0.36µs
– Try to push the limits, fc = 220 kHz …
Quantization effect disturbances!
ECEN5807
53