Sequential Circuit Design
Design Procedure
1.
2.
Specification
Formulation

3.
State Assignment

4.
Optimize the equations
Technology Mapping

8.
Derive output equations from output entries in the table
Optimization

7.
Select flip-flop types and derive flip-flop equations from
next state entries in the table
Output Equation Determination

6.
Assign binary codes to the states
Flip-Flop Input Equation Determination

5.
Obtain a state diagram or state table
Find circuit from equations and map to flip-flops and gate
technology
Verification

Verify correctness of final design
2
Typical Sequential Circuit
C1
x(t)
present
inputs
s(t+1)
next
state
State Register
Mealy Machine
s(t)
present
state
C2
z(t)
clock
3
Typical Sequential Circuit
x
Q
A
C Q
A’
Q
B
D
Example
Next State
D
CP
C Q'
y
Output
4
Sequence Detector
•
101 sequence Detector
X
=
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
Z
=
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
(time:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15)
5
Design of 101 Sequence Detector
•
State Diagram:
1/0
6
Design of 101 Sequence Detector
•
State Diagram (final):
7
Design of 101 Sequence Detector
•
State Table:
Present
Output
Present
state
X=0
X=1
X=0
X =1
S0
S1
S2
S0
S2
S0
S1
S1
S1
0
0
0
0
0
1
•
Next State
State Table with State Assignment:
DA DB
A+ B+
Z
AB
X=0
X=1
X=0
X =1
00
01
10
00
10
00
01
01
01
0
0
0
0
0
1
8
Design of Sequence Detector
•
Derive Boolean Equations:
A
AB
00
01
11
10
0
0
1
X
0
1
0
0
X
0
X
B
DA = X’.B
A
AB
00
01
11
10
0
0
0
X
0
1
1
1
X
1
X
B
DB = X
Z = X.A
A
AB
00
01
11
10
0
0
0
X
0
1
0
0
X
1
B
9
C1
Compare with Typical
Mealy Machine
x(t)
present
inputs
s(t+1)
next
state
State Register
Design of Sequence Detector
clock
s(t)
present
state
C2
z(t)
10
Design of Sequence Detector
C1
x(t)
present
inputs
s(t+1)
next
state
State Register
• A Moore Sequence Detector:
s(t)
C2
z(t)
present
state
clock
11
Sequence Detector
•
101 sequence Detector
X
=
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
Z
=
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
(time:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15)
12
Design of a Sequence Detector
S0: start
S1: got 1
S2: got 10
S3: got 101
13
Design of a Sequence Detector
S0: start
S1: got 1
S2: got 10
S3: got 101
14
Design of a Sequence Detector
State Table
Transition Table with State
assignment
Prese
nt
state
Next State
X=0
X=1
Present
Output (Z)
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
DA DB
A+ B+
AB
X=0
X=1
Z
00
01
11
10
00
11
00
11
01
01
10
01
0
0
0
1
15
State Assignment
Each of the m states must be assigned a
unique code.
Minimum number of bits required is n such
that
n ≥ log2 m
where x is the smallest integer ≥ x.
There are 2n - m unused states.
(There are useful state assignments that
use more than the minimum number of
bits).
17
State Assignment: Example 2
Present
State
A
B
C
D
Next State
x=0 x=1
A
B
A
C
D
C
A
B
Output
x=0 x=1
0
0
0
0
0
0
0
1
How may assignments of codes with a
minimum number of bits?
4  3  2  1 = 24
Does code assignment make a difference in
cost?
31
State Assignment: Example 2
Assignment 1:
A = 0 0, B = 0 1, C = 1 0, D = 1 1
The resulting coded state table:
Next State
Present
State x = 0 x = 1
00
01
10
11
00
00
11
00
01
10
10
01
Output
x=0x=1
0
0
0
0
0
0
0
1
32
State Assignment: Example 2
Assignment 2:
A = 0 0, B = 0 1, C = 1 1, D = 1 0
The resulting coded state table:
Present
State
00
01
11
10
Next State
x=0x=1
00
00
10
00
01
11
11
01
Output
x=0x=1
0
0
0
0
0
0
0
1
33
Flip-Flop Input and Output
Equations: Example 2 (version 1)
Assume D flip-flops
Interchange the bottom two rows of the state
table, to obtain K-maps for DA, DB, and Z:
A
AB
00
01
11
10
0
0
0
0
1
1
0
1
0
1
X
A
AB
B
DA = A.B’ + X.A’.B
00
01
11
10
0
0
0
0
1
1
1
0
1
0
X
B
DB = X’.A.B’ + X.A’.B’+X.A.B
34
Flip-Flop Input and Output
Equations: Example 2 (version 1)
A
AB
00
01
11
10
0
0
0
0
0
1
0
0
1
0
X
B
Z = A.B.X
Gate Input Cost = 22
35
Flip-Flop Input and Output
Equations: Example 2 (version 2)
Assume D flip-flops
Interchange the bottom two rows of the state
table, to obtain K-maps for DA, DB, and Z:
A
AB
00
01
11
10
0
0
0
1
0
1
0
1
1
0
X
A
AB
00
01
11
10
0
0
0
0
0
1
1
1
1
1
X
B
DA = A.B + X.B
B
DB = X
36
Flip-Flop Input and Output
Equations: Example 2 (version 2)
A
AB
00
01
11
10
0
0
0
0
0
1
0
0
0
1
X
B
Z = A.B’.X
Gate Input Cost = 9
Select this state assignment
37
Implementation
 Initial Circuit:
• Library:
 D Flip-flops
with Reset
(not inverted)
 NAND gates
with up to 4
inputs and
inverters
Y1
D
C
R
Z
X
Clock
Y2
D
C
R
Reset
38
Technology Mapping
Y1
D
C
R
Z
Y2
X
Clock
D
C
R
Reset
39
Example : Vending Machine
•
General Machine Concept:



Deliver package of gum after 15 cents
deposited
Single coin slot for dimes (10¢) , nickels (5¢)
No change
40
Example : Vending Machine
•
Step 1: Understand the problem:

Draw a picture
5¢
Coin
Sensor
10¢
Reset
Vending
Machine
FSM
Open
Gum
Release
Mechanism
Clk
41
Example : Vending Machine
• Step 2: Draw state diagram:
 All possible sequences
Reset
 Inputs: N, D, reset
S0
 Output: open
N
S1
D
S2
Dime: 10¢
N
Nickel: 5¢
N
N
D
S4
S5
S6
[open]
[open]
[open]
S3
• Notes:
 If neither N nor D,
goes to itself.
 Both N and D is not
possible.
D
D
S7
S8
[open]
[open]
42
Example : Vending Machine
• Step 3: State minimization:
 reuse states whenever possible
Reset
0¢
N
5¢
Dime: 10¢
D
N
Nickel: 5¢
10¢
D
N, D
15¢
[open]
43
Example : Vending Machine
• Step 4: Symbolic State table:
Present
State
Reset
0¢
0¢
N
5¢
D
5¢
N
10¢
10¢
D
N, D
15¢
[open]
15¢
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
Next
State
Output
Open
0¢
5¢
10¢
X
5¢
10¢
15¢
X
10¢
15¢
15¢
X
15¢
0
0
0
X
0
0
0
X
0
0
0
X
1
From 15¢ state, you may want to go to reset state
44
Example : Vending Machine
• Step 5: State encoding:
Present State Inputs
Q1 Q0
D N
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State
D 1 D0
Output
Open
0 0
0 1
1 0
X X
0 1
1 0
1 1
X X
1 0
1 1
1 1
X X
1 1
1 1
1 1
X X
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
45
Example : Vending Machine
• Step 6: Choose FF for implementation:
 DFF easiest
Q1
Q1 Q0
DN
0
D
0
1
1
0
1
1
1
X
X
X
X
1
1
1
1
0
1
Q0
N
D1
CLK
R
Q1
N
Q1
D
0
0
0
1
0
0
1
1
0
0
1
0
X
X
X
X
0
1
1
1
Q
Q1
Q
\ Q1
N
D
OPEN
D
CLK
R
\reset
Q
Q0
Q
\ Q0
X
X
X
X
0
0
1
0
Q0
K-map for Open
D1 = Q1 + D + Q0 N
\reset
D0
1
N
D
N
\ Q0
Q0
\N
1
Q0
K-map for D0
D
Q1
Q1 Q0
DN
N
Q0
K-map for D1
Q1
D
Q1
Q1 Q0
DN
D0 = N Q0’ + Q0 N’ + Q1 N + Q1 D
OPEN = Q1 Q0
8 Gates
46
Using Other FFs for Design
•
Characteristic Table:
 defines the next state of the flip-flop in
terms of flip-flop inputs and current state.
 Used in Circuit Analysis
•
Excitation Table:
 defines the flip-flop input variable values
as function of the current state and next
state.
 Used in Circuit Design
48
SR FF Tables
•
Characteristic Table:
S R Q(t +1) Operation
•
0 0
0 1
1 0
Q(t)
0
1
No change
Reset
Set
1 1
?
Undefined
Excitation Table:
Q(t)
Q(t+ 1)
S R
Operation
0
0
1
0
1
0
0 X
1 0
0 1
No change / Reset
1
1
X 0
No change / Set
Set
Reset
49
DFF Tables
•
Characteristic Table:
D
Q(t + 1) Operation
0
1
•
0
1
Reset
Set
Excitation Table:
Q(t)
Q(t +1)
D
Operation
x
x
0
1
0
1
Reset
Set
50
JK FF Tables
•
•
Characteristic Table:
J K Q(t+1)
Operation
0
0
1
1
No change
Reset
Set
Complement
0
1
0
1
Q(t)
0
1
Q(t)
Excitation Table:
Q(t)
0
0
1
1
Q(t+1) J K Operation
0
1
0
1
0
1
X
X
X
X
1
0
No change / Reset
Set / Toggle
Reset / Toggle
No Change / Set
51
T FF Tables
•
•
Characteristic Table:
T Q(t+1)
Operation
0
Q(t)
No change
1
Q(t)
Complement
Excitation Table:
Q(t)
0
0
1
1
Q(t+1) T
0
1
0
1
0
1
1
0
Operation
No change
Toggle
Toggle
No Change
52
Example
•
Design by DFF
53
Example
A(t + 1) = DA(A,B,X) =  m(2,4,5,6)
B(t + 1) = DB(A,B,X) =  m(1,3,5,6)
Y(A,B,X) =  m(1,5)
A
BX
00
0
1
1
01
11
1
A
10
1
1
BX
00
0
1
DA = AB + BX
01
1
1
11
1
10
1
DB = AX + BX + ABX
BX
A
00
0
1
01
1
1
11
10
Y = BX
54
Example

Logic Diagram for Circuit with D Flip-Flops
55
Example
•
Q(t)
Design by JK FF
Q(t+1)
J
K
Operation
0
0
0
X
No change/reset
0
1
1
X
Set/Toggle
1
0
X
1
Reset/Toggle
1
1
X
0
No Change/set
 Don’t cares
 lead to simpler
combinational circuit
56
Example: Boolean Equations
JA = BX
KA = BX
JB = X
KB = AX + AX
57
Example: Logic Diagram
58