Engineering 43
Logic Circuit
Synthesis
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
[email protected]
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
ReCall the Basic Gates
Engineering-43: Engineering Circuit Analysis
2
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Boolean Logic

The Logical Operators Form The Basis of
BOOLEAN (Two Value, T & F, 1 & 0,
Hi & Lo, Up & Dwn, Left & Right, etc.) Logic
•

Developed by George Boole (1815-1864)
The Action of the Boolean Operators are
Often Characterized with TRUTH Tables
AND (all high = high, else low)
NOT (inverter)
Input 1
Input 2
Output
Input 1
Input 2
Output
Input = 1 Output = 0
0
0
0
0
0
0
Input = 0 Output = 1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
1
1
Engineering-43: Engineering Circuit Analysis
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OR (any high = high, else low)
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Boolean Algebra
 Boolean Logic can be Mathematically
Formalized with the use of Math Operators
 The Math Operators Corresponding to
Boolean Logic Operations:
Operator
Usage
Notation
AND
A AND B
A.B or A·B
OR
NOT
A OR B
NOT A
A+B
~A or A or A’
• A and B can only be TRUE or FALSE
• TRUE represented by 1; FALSE by 0
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Boolean Algebraic Properties
 Commutative: A.B = B.A and A+B = B+A
 Distributive:
• A.(B+C) = (A.B) + (A.C)
• A+(B.C) = (A+B).(A+C)
 Identity Elements: 1.A = A and 0 + A = A
 Inverse: A.A = 0 and A + A = 1
 Associative:
• A.(B.C) = (A.B).C and A+(B+C) = (A+B)+C
 DeMorgan's Laws:
• A.B = A + B
• A+B = A.B
Engineering-43: Engineering Circuit Analysis
5
NAND
NOR
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Prove Distributive Law
 ReCall Bolean
Distributive Law
AB  C   AB  AC
 Do The Circuits at
Right Implement The
Sides of this Identity?
 If the Identity is
TRUE, then the
TruthTable for
BOTH circuits must
be Identical
Engineering-43: Engineering Circuit Analysis
6
D
A∙(B+C)
¿Same?
D
(A∙B)+(A∙C)
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Prove Distributive Law
 Constructing a Truth Table that Includes
and Expands [AB+AC] & [A(B+C)]
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C B+C AB AC AB+AC A(B+C)
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
IDENTICAL
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Prove XOR distributive Law
 A Truth Table Also Proves
the EXCLUSIVE-OR A.(BC) ≡ A.BA.C
Version of the Dist Law
A B C BC AB AC ABAC A(BC)
0 0 0
0
0
0
0
0
0 0 1
1
0
0
0
0
0 1 0
1
0
0
0
0
0 1 1
0
0
0
0
0
1 0 0
0
0
0
0
0
1 0 1
1
0
1
1
1
1 1 0
1
1
0
1
1
1 1 1
0
1
1
0
0
IDENTICAL
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
DeMorgan in MATLAB
 DeMorgan → Case-a:  A  B   A  B
?
>> % case-a
>> x = 7
x =
1
1
7
>> a1 = ~((x < 10)&(x >= 6))
a1 =
0
0
0
>> a2 = (~(x < 10))|(~(x >= 6))
a2 =
0
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
DeMorgan in MATLAB
 DeMorgan → Case-b
A  B  A  B
?
>> % case-b
>> y = 3
y =
0
0
3
>> b1 = ~((y == 2)|(y > 5))
b1 =
1
1
1
>> b2 = (~(y == 2))&(~(y >5))
b2 =
1
Engineering-43: Engineering Circuit Analysis
10
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Multiple-Input Gates
 The Flexibility of
Boolean Algebra
permits Straight
Forward Extension
to Gates with Many
Inputs
All Hi = Hi;
Else Lo
Engineering-43: Engineering Circuit Analysis
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 The Number of
Entries in the Truth
Table is 2N, where:
• N ≡ No. of INputs
All Hi = Hi;
Else Lo
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Gates  Boolean
 Write the Boolean Expression
Equivalent to the Logic Circuit Analyzed
Last Lecture
CD
Q
CD
A  B D  C D  C  D  Q
A BD
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Boolean  Gates (WhiteBoard)
 Draw the Logic-Gate Circuits to
Implement these Boolean Equations
• Use Multiple-Input Gates as desired
Q1   A  B  C   A  B  C 
Q2  B  C  D  A  C  D  C  D 
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
One Solution to Previous Sld
B+C+D’
 A Product of Sums
(PoS)
Implementation
A+C+D’
C’+D
Q2  B  C  D  A  C  D  C  D 
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Principal Boolean Algebra Laws
OR expression
AND expression
0+a=a
1a = a
1+a=1
0a = 0
a+a=a
aa = a
a + a' = 1
aa' = 0
(a')' = a
a+b=b+a
ab = ba
a +(bc) = (a + b)(a + c)
a(b + c) = ab + ac
a + (b + c) = (a + b) + c
a(bc) = (ab)c
a + ab = a
a(a + b) = a
a + a'b = a + b
a(a' + b) = ab
( a + b)' = a' b'
(ab)' = a' + b'
ab + a'c + bc = ab + a'c (a+b)(a'+c)(b+c) = (a+b)(a'+c)
NOTE:
Engineering-43: Engineering Circuit Analysis
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a'  a
b'  b
Law Name
Identity
Idempotency
Complement
Involution
Commutativity
Distributivity
Associativity
Absorption
Simplification
DeMorgan's Law
Consensus Thrm
etc.
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
MinTerms  Sum of Products
 Consider an Example  Function Notation
Boolean function of
• X, Y, Z → Inputs
three variables by
• Q → Output
Truth Table (TT)
 The only non-zero
X Y Z Q
OutPuts occur at:
0 0 0 0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
0
0
Engineering-43: Engineering Circuit Analysis
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• X = 0, Y = 1, Z = 0
• X = 1, Y = 0, Z = 1
 The Fcn is 1 for
those 2 input-sets
and 0 for all other
input conditions.
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
MinTerms  Sum of Products
 The Function
Operation Requires
• The output to be 1
whenever
– X=0 AND Y=1 AND
Z=0
• OR when
– X=1 AND Y=0 AND
Z=1
 This Description can
be written using
Boolean Algebra:
Engineering-43: Engineering Circuit Analysis
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X
0
0
0
0
1
1
1
1
Y
0
0
1
1
0
0
1
1
Z
0
1
0
1
0
1
0
1
Q  X Y  Z  X Y  Z
 Function read as:
(NOT-X AND Y
AND NOT-Z) OR (X
AND NOT-Y AND Z)
 By Way of
• NOT-X = 0
• NOT-Y = 0
• Etc.
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Q
0
0
1
0
0
1
0
0
MinTerms  Sum of Products
 The Ckt Below
Implements Fcn:
Q  X Y  Z  X Y  Z
Q
Engineering-43: Engineering Circuit Analysis
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 The function is
composed of two
groups of three.
X
0
0
0
0
1
1
1
1
Y
0
0
1
1
0
0
1
1
 Each group of three is
called a minterm.
• minterm implies that
each of the groups of
3 in the expression
takes on a value of 1
only for one of the 8
possible combos of X,
Y and Z and their
inverses Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Z
0
1
0
1
0
1
0
1
Q
0
0
1
0
0
1
0
0
MinTerms  Sum of Products
 Important points about minterms include
the following.
1. In a minterm, each variable, X, Y or Z
appears once, either as the variable
itself or as the inverse.
X Y Z Q
0 0 0 0
2. Each minterm corresponds 0 0 1 0
0 1 0 1
to exactly one entry (row!) 0 1 1 0
1 0 0 0
in the truth table.
• The Rows with Output = 1
Engineering-43: Engineering Circuit Analysis
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1
1
1
0
1
1
1
0
1
1
0
0
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Boolean Eqn from TruthTable
 It turns out that ANY Boolean function can be
constructed using minterms
 To build a Boolean fcn from minterms:
1. Examine the truth table for the function.
–
Be sure that all possible combinations of variables and
inverses are accounted for.
2. For each entry of the truth table for which the Function
takes on a value of 1, determine the corresponding
minterm expression (an AND expression)
–
Remember that EVERY variable or its inverse will appear in
EVERY minterm.
3. OR (add) Together all the minterms from step-2
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
MinTerms & SOP Summarized
 We can sum up the MinTerm
Construction with the following:
 A truth table gives a unique
Sum-Of-Products function
that follows directly from
expanding the ones in the
truth table as minterms.
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
MinTerms Example
 Construct Fcn for
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
V
0
0
0
1
0
1
1
1
 ID the Rows with
ONES for minterms
Engineering-43: Engineering Circuit Analysis
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A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
V
0
0
0
1
0
1
1
1
 Thus This Function
has a Total of FOUR
MinTerms
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
MinTerms Example
 T1 product is the
First MinTerm by
Multiplication
T1  A  B  C
 Similarly Construct
Terms 2-4 by
Multiplication
T2  A  B  C
T4  A  B  C
23
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
V
0
0
0
1
0
1
1
1
 To Write the V(ABC)
Function Simply OR
(add) the MinTerms
V
A  B  C    A  B  C  
A  B  C    A  B  C 
T3  A  B  C
Engineering-43: Engineering Circuit Analysis
A
0
0
0
0
1
1
1
1
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
A
0
0
0
0
1
1
1
1
MinTerms Example
 The Ckt Fragment
for the 1st minterm
T1  A  B  C
 The Ckts for the
other Three
minterms:
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
V
0
0
0
1
0
1
1
1
MinTerm Example
 OR-ing the
MinTerms
Completes the
Function:
V
V
A  B  C    A  B  C  
A  B  C    A  B  C 
 This amounts to
Connecting the
4 ckt-fragments
to an OR gate
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Sum-of-Products Summarized
 one or more AND gates feeding a
single OR gate at the output
 Example: AB '  CD ' E  AC ' E '  Q
A
B'
C
D'
E
A
C'
E'
Engineering-43: Engineering Circuit Analysis
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Q
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
PRODUCT of SUMS summarized
 One or more OR gates feeding a single
AND gate at the output
• The DUAL of SUM of PRODUCTS
( A  B ' )  (C  D '  E )  ( A  C '  E ' )  Q
A
B'
C
D'
E
A
C'
E'
Engineering-43: Engineering Circuit Analysis
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Q
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Prod-of-Sums  MaxTerms
 Use MaxTerms to
Write the Boolean
Equation for
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Q
1
0
1
0
0
0
1
1
Engineering-43: Engineering Circuit Analysis
28
 ID rows with OutPut
of ZERO
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Q
1
0
1
0
0
0
1
1
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Prod-of-Sums  MaxTerms
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
 Note for a SUM (OR)
to be Zero All terms
MUST Be Zero
A  B  C   0  0  0  0
 Examine the 2nd row
A  B  C   0  0  0  0
A  B  C   0  0  0  0
A  B  C   0  0  0  0
A
0
0
0
B
0
0
1
C
0
1
0
Q
1
0
1
 For A, B, & C to Add
to ZERO Need
Engineering-43: Engineering Circuit Analysis
29
 Similarly for the
other ZERO Rows
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
C
0
1
0
1
0
1
0
1
Q
1
0
1
0
0
0
1
1
Prod-of-Sums  MaxTerms
 Thus ANDing (multiplying) the
MaxTerms ENSURES that Q will ZERO
if any ONE of the MaxTerms is Zero.
 Thus the Function Q
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
Q  A  B  C  A  B  C  A  B  C  A  B  C 
 A (different)
P.O.S. Ckt
Fragment
Engineering-43: Engineering Circuit Analysis
30
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
C
0
1
0
1
0
1
0
1
Q
1
0
1
0
0
0
1
1
A
0
0
0
0
1
1
1
1
Prod-of-Sums  MaxTerms
 The Logic Circuit for the Example
Q
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Q
1
0
1
0
0
0
1
1
SOP & MINterms ShortHand
Row
 Consider the Fcn
0
1
 Written in SOP
2
Form
3
Q  A B C  A BC  ABC
4
 Notice the function 5
6
consists of
7
minterms from
rows 0, 2, and 6
 Thus the ShortHand
Q  m0  m2  m6
Engineering-43: Engineering Circuit Analysis
32
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
minterm
Q
1 → A’∙B’∙C’
0
1 → A’∙B∙C’
0
0
0
→ A∙B∙C’
1
0
 In Even ShorterHand
Q   m0,2,6
• Quickly ID’s the
MinTerms
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
POS & MAXTerms ShortHand
Row
 Consider the Fcn
0
1
 Written POS
2
Form
3
Q  A  B  C A  B  C A  B  C 
4
 Notice the function 5
6
consists of
7
maxterms from
rows 3, 4, and 7
 Thus the ShortHand
Q  M3  M4  M7
Engineering-43: Engineering Circuit Analysis
33
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
maxterm
Q
1
1
1
0 → A+B’+C’
→ A’+B+C
0
1
1
0 → A’+B’+C’
 In Even ShorterHand
Q   M 3,4,7
• Quickly ID’s the
MaxTerms
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
SOP & POS Summarized
 Sum-of-Products (SOP or minterms)
• first the product (AND) terms are formed
then, second, these are summed (OR)
• e.g.: (A∙B∙C) + (D∙E∙F) + (G∙H∙I) = 1
 Product-of-Sums (POS or maxterms)
• first the sum (OR) terms are formed then,
second, the products are taken (AND)
• e.g.:(A+B+C)∙(D+E+F)∙(G+H+I) = 0
 Convert Between forms using DeMorgan
Engineering-43: Engineering Circuit Analysis
34
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Canonical Form
 Canonical form is not usually an
efficient description of a Boolean
function but it is sometimes useful in
analysis and design
 In an expression in Canonical form,
every Variable appears in every Term
(for SoP) or Factor (for PoS), e.g.:
f SOP  A, B, C, D   A B C D  A BC D  ABCD
f POS  A, B, C, D   A  B  C  D  A  B  C  D   A  B  C  D 
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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SOP  Canonical
 Any SOP expression can be forced into
canonical form by ANDing the
incomplete terms with terms of the Form
(X+X’) where X is the name of the
missing variable, e.g.:
Q A, B, C  
ReCall a+a’=1
by
Complement Law
AB  BC

AB  C  C   A  A  BC

ABC  ABC  ABC  A BC

ABC  ABC  A BC
 This operation produces the minterms
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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MINIMUM: SOP (1’s) & POS (0’s)
 The minimum sum of products (MSOP) of a function, f, is a SOP
representation of f that contains the fewest number of product terms
and fewest number of literals (Variable-Instances) of any SOP
representation of f.
 Example -- f(a,b,c,d) = m(3,7,11,12,13,14,15)
MINterms →
= ab + acd + acd
Fewer Addition Signs
= ab + cd
 The minimum product of sums (MPOS) of a function, f, is a POS
representation of f that contains the fewest number of sum terms
and the fewest number of literals of any POS representation of f.
 Example -- f(a,b,c,d) = M(0,1,2,4,5,6,8,9,10)
= (a + c)(a + d)(a + b + d)(b + c + d)
= (a +c)(a + d)(b + c)(b + d)
MAXterms → More Addition Signs
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Karnaugh Maps
 Karnaugh maps (K-maps) → convenient
tool for representing switching (logic)
functions of up to six variables.
 K-maps form the basis of useful
heuristics (algorithms) for finding MSOP
and MPOS representations.
 An n-variable K-map has 2n cells with
each cell corresponding to a row of an
n-variable truth table.
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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Karnaugh Maps
 K-map cells are labeled with the
corresponding truth-table row.
 K-map cells are arranged such that
adjacent cells correspond to truth rows
that differ in only one bit position (logical
adjacency, or GRAY-code form)
 Switching functions are mapped (or
plotted) by placing the function’s value
(0,1,d) in each cell of the map.
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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Karnaugh Map Example
 An Example of a 4
Variable Karnaugh
Map
AB\CD 00
CD
01 11
00
01
A  B C  D
 The Square Marked
▼ represents
A  B C  D
▲
▼
AB
11
01
Engineering-43: Engineering Circuit Analysis
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01
 The Square Marked
▲ represents
 Note the two
marked Squares
differ only in the
(one) C Variable
• The GRAY format
Bruce Mayer, PE
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What is GRAY code sequence?
 Gray code sequence only changes one
bit as we go from one number to the
next in the sequence, unlike binary.
 Adjacent cells vary
by only one bit
because a Gray
code sequence
varies by only
one bit.
Engineering-43: Engineering Circuit Analysis
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Karnaugh Map MiniMization
 Write the Boolean expression in SOP,
or minterms, form
 For each product term, write a 1 in all
the squares which are included in the
term, 0 elsewhere
• canonical form: one square
• one term missing: two adjacent squares
• two terms missing: 4 adjacent squares
Engineering-43: Engineering Circuit Analysis
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Karnaugh Map MiniMization (SOP)
 Example: Q  A BC  AB C  ABC  ABC
 1  1  1  1
A\BC 00 01 11 10
 Then the
K-map
0 0
0
1
0
 The meaning
of the 1’s
• Products
Used in
the SOP
Expression
Engineering-43: Engineering Circuit Analysis
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1
0
1
1
1
A\BC 00
01
11
10
0
0
0
A’BC
0
1
0
AB’C
ABC
ABC’
Bruce Mayer, PE
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Karnaugh Map MiniMization
 Minimization is done by recognizing patterns
of 1's and 0's
 Basic Boolean theorems are then used to
simplify the Boolean description of the patterns
 Pairs of adjacent 1's
• remember that adjacent squares differ by only one
variable
• hence the combination of
P A A
2 adjacent squares has the form
CRITICAL
• this can be simplified to just P as
P∙(0+1) = P∙(1+0) = P by Boolean Algebra

Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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
Karnaugh Map Example (SOP)
 The Previous K-map
A\CD
A/BC 00
01
11
10
0
0
0
1
0
1
0
1
1
1
 Note ADJACENT
Squares at “11”
 The adjacent Sqs
A’B∙C and
A∙B∙C differ
ONLY in A
• hence they can be
combined into just BC
• normally indicated by
grouping the adjacent
• Boxing In the
squares subject to
Vertical Adjacency
combination
𝐴∙𝐵∙𝐶 + 𝐴∙𝐵∙𝐶 = 𝐵∙𝐶 𝐴+𝐴 = 𝐵∙𝐶 1 = 𝐵∙𝐶
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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Adjacent Pairs (SOP or minterms)
 Again: Q  A BC  AB C  ABC  ABC
 “Cover” all the 1’s A\BC 00 01 11 10
0 0
0
1
0
with “maximum”
Varies Only
grouping:
1
1
1
by “A” 1 0
 The simplified (BC group)
Eqn is one that Varies Only
Varies Only
by “B”
by “C”
Sums All Terms
(AC group)
(AB group)
corresponding to
each of the groups: 𝑄 = 𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Wrap-Around Adjacency
 The Top/Bot and Left/Right Edges of
the K-maps are Adjacent as well
• Think of Map being “Rolled Up”
Only C’ does not change
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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Karnaugh Map Simplification
 The K-Map uses the following rules for
simplification of expressions by
grouping together adjacent cells
containing ones
1. Groups may NOT include any cell
containing a ZERO
Engineering-43: Engineering Circuit Analysis
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Karnaugh Rules (SOP)
2. Groups may be horizontal or vertical,
but not diagonal
3. Groups must contain 1, 2, 4, 8, or in
general 2n cells (need “Square Boxes”)
•
That is if n = 1, a group will contain two
1's since 21 = 2. If n = 2, a group will
contain four 1's since 22 = 4, etc.
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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Grouping ProtoCol
Engineering-43: Engineering Circuit Analysis
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Karnaugh Rules
4. Each group should be as large as
possible
5. Each cell
containing
a one must
be in at least
one group
Engineering-43: Engineering Circuit Analysis
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Better for
Minimization
Bruce Mayer, PE
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Karnaugh Rules
6. Groups Should
OverLap
if Possible
7. Groups May
“Wrap-Around”
•
Top↔Bot
•
Left↔Right
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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Karnaugh Rules
8. There should be as few groups as
possible, as long as this does not
contradict any of the previous rules.
•
i.e.; Map for Maximum OverLap
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Karnaugh Rule Summary
1. No zeros allowed.
2. No diagonals.
3. Only power-of-2 number of cells in each
group.
4. Groups should be as large as possible.
5. Every ONE must be in at least one group.
6. OverLapping allowed (and Best).
7. Wrap-Around allowed (and Best).
8. Fewest number of groups possible
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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4-Var K-Map Examples (SOP)
C&D Change,
A&B Change,
A&C Change, D Changes, ABC
AB Same → AB C’D Same → C’D BD’ Same → BD’ Same → ABC
a WrapAround
Q  AB  C D
Engineering-43: Engineering Circuit Analysis
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Q  ABC  BD
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Even More
Complicated
Examples
 Eliminate the
letters that
CHANGE
Across the
Group (if the
group is >1)
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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“don’t care” Conditions
 In certain cases some of the minterms may
never occur or it may not matter to the
LOGIC OPERATION what they they are
 In such cases we fill in the Karnaugh map
with an X (or d) to mean “don't care”
 When minimizing an X is like a "joker“
• X can be 0 or 1; Which Ever Helps Minimization
A\BC 00 01 10 11
 e.g. this
00
0
• With d = 1
Simplifies to Q = B 01 0
Engineering-43: Engineering Circuit Analysis
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0
1
d
0
1
1
Bruce Mayer, PE
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d set by the
DESIGNER
Don’t Care Examples
 “Don’t care” conditions should be
changed to either 0 or 1 to produce
K-map Grouping that yields the simplest
expression.
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
All Done for Today
Maurice
Karnaugh
& a Map
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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Engineering 43
Appendix
NAND
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
[email protected]
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[email protected] • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
what
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
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