Digital System Design
Verilog:
Blocks, Conditional Statement, Loops
Dr. Bassam Jamil
Topics
 always
 initial
block
Block
 fork/join
 Conditional
Statements
 Loops
2
Block Types
3
4
always and initial block syntax
 Initial
block syntax:
Initial begin
statement1;
statement2;
….
End
OR
Initial
statement;
 always
block syntax
always @ ( sensitivity list) begin
….
end
OR
always @ ( * )
begin …. end
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Initial Block
6
Initial Block Example
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always Block
module clock_gen
reg _clk;
initial
clk = 1’b0;
always @ (clk)
#10 clk = ~ clk ;
initial begin
#1000 $finish;
end
endmodule
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always Block
module clock_gen
reg _clk;
initial
clk = 1’b0;
always @ (clk)
#10 clk = ~ clk ;
initial begin
#1000 $finish;
end
endmodule
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More always Block Examples
Always Block Examples
Notes
always @(a or b or ci)
begin
sum = a + b + ci;
end
always block executes
statements repeatedly.
always @(posedge clk)
q <= data;
always block executes when
clock changes from 0 to 1
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Conditional Statements
 If
statement syntax:

if (expression) statement or statement_group

if (expression) statement or statement_group
else statement or statement_group
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Conditional Statements: Nested If
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Conditional Statements: Multi-way If
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Conditional Statements: case statement
 Case
syntax
case (net_or_register_or_literal)
case_match1: statement or statement_group
case_match2,
case_match3: statement or statement_group
default: statement or statement_group
endcase
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Conditional Statements: casex/casez
 casez

Special version of the case statement which uses a Z
logic value to represent don't-care bits.
 casex

(net_or_register_or_literal)
(net_or_register_or_literal)
Special version of the case statement which uses Z or
X logic values to represent don't-care bits.
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Conditional Statements: case statement
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Loop Statements
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Forever
Syntax:
reg clk;
forever statement or statement_group
Initial begin
clk = 0;
forever #10 clk = ~ clk;
end
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Repeat
Syntax:
repeat (number)
statement or
statement_group
Wait for
5 clocks
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While Statement
Syntax:
while (expression)
statement or
statement_group
Count number of 1’s in
register in
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For Statement
Sntax:
for (initial_assignment;
expression;
step_assignment)
statement or statement_group
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Parallel Statements
Syntax:
fork
statement1;
All statements
statement2;
start at the
…
same time.
statementN;
join
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Parallel Statements
begin/end and fork/join blocks
have same effect
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Named Block and disable statement
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Mux4 Modeling
 Will
model the mux4 in various modeling styles:

Structural
Behavioral Continuous Assignment

Behavioral Procedural using if statement

Behavioral Procedural using case statement

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Structural to Behavioral
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Mux 4 Behavioral (Cont. assign)
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Mux4 Example
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