Sequential CPU
Implementation
Suggested Reading
- Chap 4.3
–2–
Processor
Y86 Instruction Set
Byte
0
nop
0
0
halt
1
0
rrmovl rA, rB
2
0 rA rB
irmovl V, rB
3
0
8 rB
V
rmmovl rA, D(rB)
4
0 rA rB
D
mrmovl D(rB), rA
OPl rA, rB
jXX Dest
call Dest
ret
pushl rA
popl rA
–3–
5
1
2
P259
3
0 rA rB
4
5
addl
6
0
subl
6
1
andl
6
2
xorl
6
3
jmp
7
0
jle
7
1
jl
7
2
je
7
3
jne
7
4
jge
7
5
jg
7
6
D
6 fn rA rB
7 fn
8
9
A
B
0
Dest
Dest
0
0 rA 8
0 rA 8
Processor
Building Blocks P278, P279,
P280
fun
Combinational Logic






–4–
Store bits
Addressable memories
Non-addressable registers
Loaded only as clock rises
=
A
L
U
Compute Boolean functions of
inputs
B
Continuously respond to input
changes
Operate on data and implement
control
Storage Elements

A
0
MUX
1
valA
srcA
A
valW
Register
file
valB
srcB
B
W
dstW
Clock
Clock
Processor
Hardware Control Language


Very simple hardware description language
Can only express limited aspects of hardware operation
 Parts we want to explore and modify
Data Types

bool: Boolean
 a, b, c, …

int: words
 A, B, C, …
 Does not specify word size---bytes, 32-bit words, …
Statements

bool a = bool-expr ;
 int A = int-expr ;
–5–
Processor
HCL Operations

Classify by type of value returned
Boolean Expressions

Logic Operations
 a && b, a || b, !a

Word Comparisons
 A == B, A != B, A < B, A <= B, A >= B, A > B

Set Membership
 A in { B, C, D }
» Same as A == B || A == C || A == D
Word Expressions

Case expressions
 [ a : A; b : B; c : C ]
 Evaluate test expressions a, b, c, … in sequence
 Return word expression A, B, C, … for first successful test
–6–
Processor
4.3.1
Instruction Execution Stages
P281
Fetch

Read instruction from instruction memory
Decode

Read program registers
Execute

Compute value or address
Memory

Read or write data
Write Back

Write program registers

Update program counter
PC
–7–
Processor
Instruction Decoding
Optional
5
0 rA rB
Optional
D
icode
ifun
rA
rB
valC
Instruction Format



–8–
Instruction byte
icode:ifun
Optional register byte
rA:rB
Optional constant word valC
Processor
Figure 4.16 P283
Executing Arith./Logical Operation
OPl rA, rB
Fetch

Memory
Read 2 bytes
Decode

Read operand registers
Execute
–9–
6 fn rA rB

Perform operation

Set condition codes

Do nothing
Write back

Update register
PC Update

Increment PC by 2
Processor
Stage Computation: Arith/Log. Ops
P283
Figure 4.16
icode:ifun  M1[PC]
Read instruction byte
rA:rB  M1[PC+1]
Read register byte
valP  PC+2
Compute next PC
valA  R[rA]
Read operand A
valB  R[rB]
Read operand B
valE  valB OP valA
Perform ALU operation
Set CC
Set condition code register
Memory
Write
R[rB]  valE
Write back result
back
PC update
PC  valP
Update PC
Fetch
Decode
Execute


– 10 –
OPl rA, rB
Formulate instruction execution as sequence of simple
steps
Use same general form for all instructions
M1[PC] 表示从PC开始的内存中读取一个字节的数据。
Processor
Executing rrmovl
rrmovl rA, rB
Fetch

Memory
Read 2 bytes
Decode

Read operand register rA
Execute

– 11 –
2 0 rA rB
Do nothing

Do nothing
Write back

Update register
PC Update

Increment PC by 2
Processor
Stage Computation: rrmovl
P283
Figure 4.16
Fetch
Decode
Execute
rrmovl rA, rB
icode:ifun  M1[PC]
Read instruction byte
rA:rB  M1[PC+1]
Read register byte
valP  PC+2
Compute next PC
valA  R[rA]
Read operand A
valE  0 + valA
Perform ALU operation
*valE
Memory
Write
R[rB]  valE
Write back result
back
PC update
PC  valP
Update PC


– 12 –
Formulate instruction execution as sequence of simple
steps
Use same general form for all instructions
Processor
Executing irmovl
irmovl V, rB
Fetch

Read 6 bytes
Do nothing
Execute

– 13 –
V
Memory
Decode

3 0 8 rB
Do nothing

Do nothing
Write back

Update register
PC Update

Increment PC by 6
Processor
Stage Computation: irmovl
P283
Figure 4.16
irmovl rA, rB
icode:ifun  M1[PC]
Read instruction byte
rA:rB  M1[PC+1]
Read register byte
valC  M4[PC+2]
valP  PC+6
Read constant value
valE  0 + valC
Perform ALU operation
Memory
Write
R[rB]  valE
Write back result
back
PC update
PC  valP
Update PC
Fetch
Compute next PC
Decode
Execute


– 14 –
Formulate instruction execution as sequence of simple
steps
Use same general form for all instructions
Processor
Figure 4.17 P283
Executing rmmovl
rmmovl rA, D(rB) 4 0 rA rB
Fetch

Memory
Read 6 bytes
Decode

Read operand registers
Execute

– 15 –
D
Compute effective address

Write to memory
Write back

Do nothing
PC Update

Increment PC by 6
Processor
Stage Computation: rmmovl
P283
Figure 4.17
Fetch
Decode
Execute
Memory
Write
back
PC update

– 16 –
rmmovl rA, D(rB)
icode:ifun  M1[PC]
Read instruction byte
rA:rB  M1[PC+1]
Read register byte
valC  M4[PC+2]
Read displacement D
valP  PC+6
Compute next PC
valA  R[rA]
Read operand A
valB  R[rB]
Read operand B
valE  valB + valC
Compute effective address
M4[valE]  valA
PC  valP
(sum of the displacement and the
base register value)
Write value to memory
Update PC
Use ALU for address computation
Processor
Executing mrmovl
mrmovl D(rB),rA 5 0 rA rB
Fetch

Memory
Read 6 bytes
Decode

Read operand registers rB
Execute

– 17 –
D
Compute effective address

Read from memory
Write back

Update register rA
PC Update

Increment PC by 6
Processor
Stage Computation: mrmovl
P283
Figure 4.17
mrmovl D(rB) , rA
icode:ifun  M1[PC]
Read instruction byte
rA:rB  M1[PC+1]
Read register byte
valC  M4[PC+2]
Read displacement D
valP  PC+6
Compute next PC
valB  R[rB]
Read operand B
valE  valB + valC
Compute effective address
Memory
Write
valM  M4[valE]
Read data from memory
back
PC update
R[rA]  valM
PC  valP
Update register rA
Fetch
Decode
Execute

– 18 –
Update PC
Use ALU for address computation
Processor
Figure 4.18 P284
Executing pushl
pushl rA
Fetch

a 0 rA 8
Memory
Read 2 bytes

Decode

Read stack pointer and rA
Execute

– 19 –
Decrement stack pointer by
4
Store valA at the address of
new stack pointer
Write back

Update stack pointer
PC Update

Increment PC by 2
Processor
Stage Computation: pushl
P284
Figure 4.18
Fetch
Decode
Execute
Memory
Write
back
PC update

– 20 –
pushl rA
icode:ifun  M1[PC]
Read instruction byte
rA:rB  M1[PC+1]
Read register byte
valP  PC+2
Compute next PC
valA  R[rA]
valB  R [%esp]
Read valA
valE  valB + (-4)
Decrement stack pointer
M4[valE]  valA
R[%esp]  valE
Store to stack
PC  valP
Read stack pointer
Update stack pointer
*在write back之前实际上写入的元素在堆
栈外。
Update PC
Use ALU to Decrement stack pointer
Processor
Executing popl
popl rA
Fetch

Memory
Read 2 bytes
Decode

Read stack pointer
Execute

b 0 rA 8
Increment stack pointer by 4

Write back


Update stack pointer
Write result to register
PC Update

– 21 –
Read from old stack pointer
Increment PC by 2
Processor
Stage Computation: popl
P284
Figure 4.18
popl rA
icode:ifun  M1[PC]
Read instruction byte
rA:rB  M1[PC+1]
Read register byte
valP  PC+2
valA  R[%esp]
Compute next PC
valB  R [%esp]
Read stack pointer
valE  valB + 4
Increment stack pointer
Memory
Write
valM  M4[valA]
R[%esp]  valE
Read from stack
back
PC update
R[rA]  valM
Write back result
PC  valP
Update PC
Fetch
Decode
Execute


Update stack pointer
Use ALU to increment stack pointer
Must update two registers
 Popped value
– 22 –
Read stack pointer
在写回阶段要写两个寄存器，这两个写是有先后次序的。必须按照上面的方法进行，
因为rA可能就是%esp。具体见书P270 Practice Problem 4.5.
 New stack pointer
Processor
Figure 4.19 P284
Executing Jumps
jXX Dest
7 fn
fall thru:
XX XX
Not taken
target:
XX XX
Taken
Fetch


Memory
Read 5 bytes
Increment PC by 5
Decode

Do nothing
Execute

– 23 –
Dest
Determine whether to take
branch based on jump
condition and condition
codes

Do nothing
Write back

Do nothing
PC Update

Set PC to Dest if branch
taken or to incremented PC
if not branch
Processor
Stage Computation: Jumps
P284
Figure 4.19
Fetch
jXX Dest
icode:ifun  M1[PC]
Read instruction byte
valC  M4[PC+1]
Read destination address
valP  PC+5
Fall through address
Bch  Cond(CC,ifun)
Take branch?
PC  Bch ? valC : valP
Update PC
Decode
Execute
Memory
Write
back
PC update


– 24 –
Compute both addresses
Choose based on setting of condition codes and branch
condition
Processor
Executing call
8 0
call Dest
return:
XX XX
target:
XX XX
Fetch
Memory

Read 5 bytes

Increment PC by 5
Decode

Read stack pointer
Execute

– 25 –
Dest
Decrement stack pointer by
4

Write incremented PC to
new value of stack pointer
Write back

Update stack pointer
PC Update

Set PC to Dest
Processor
Stage Computation: call
P284
Figure 4.19
icode:ifun  M1[PC]
Read instruction byte
valC  M4[PC+1]
Read destination address
valP  PC+5
Compute return point
valB  R[%esp]
Read stack pointer
valE  valB + –4
Decrement stack pointer
Memory
Write
M4[valE]  valP
R[%esp]  valE
Write return value on stack
back
PC update
PC  valC
Set PC to destination
Fetch
Decode
Execute


– 26 –
call Dest
Update stack pointer
Use ALU to decrement stack pointer
Store incremented PC
Processor
Executing ret
9 0
ret
return:
XX XX
Fetch

Memory
Read 1 byte

Decode

Read stack pointer
Execute

Increment stack pointer by 4
Write back

Update stack pointer
PC Update

– 27 –
Read return address from
old stack pointer
Set PC to return address
Processor
Stage Computation: ret
P284
Figure 4.19
ret
icode:ifun  M1[PC]
Read instruction byte
valA  R[%esp]
Read operand stack pointer
valB  R[%esp]
Read operand stack pointer
valE  valB + 4
Increment stack pointer
Memory
Write
valM  M4[valA]
R[%esp]  valE
Read return address
back
PC update
PC  valM
Set PC to return address
Fetch
Decode
Execute


– 28 –
Update stack pointer
Use ALU to increment stack pointer
Read return address from memory
Processor
Computation Steps
Figure 4.16 P285
OPl rA, rB
Fetch
Decode
Execute
icode:ifun  M1[PC]
Read instruction byte
rA,rB
rA:rB  M1[PC+1]
Read register byte
valC
[Read constant word]
valP
valP  PC+2
Compute next PC
valA, srcA
valA  R[rA]
Read operand A
valB, srcB
valB  R[rB]
Read operand B
valE
valE  valB OP valA
Perform ALU operation
Cond code Set CC
Set condition code register
Memory
Write
valM
[Memory read/write]
back
PC update
dstM


– 29 –
icode,ifun
dstE
PC
R[rB]  valE
Write back ALU result
[Write back memory result]
PC  valP
Update PC
All instructions follow same general pattern
Differ in what gets computed on each step
Processor
Computation Steps
Figure 4.19 P284
icode,ifun
Fetch
Decode
Execute
– 30 –
Read instruction byte
[Read register byte]
valC
valC  M4[PC+1]
Read constant word
valP
valP  PC+5
Compute next PC
valA, srcA
[Read operand A]
valB, srcB
valB  R[%esp]
Read operand B
valE
valE  valB + –4
Perform ALU operation
Cond code
valM
back
PC update
dstM

icode:ifun  M1[PC]
rA,rB
Memory
Write

call Dest
dstE
PC
[Set condition code reg.]
M4[valE]  valP
R[%esp]  valE
[Memory read/write]
[Write back ALU result]
Write back memory result
PC  valC
Update PC
All instructions follow same general pattern
Differ in what gets computed on each step
Processor
Computed Values
Fetch
Execute
icode
ifun
rA
Instruction code
Instruction function
Instr. Register A
rB
valC
valP
Instr. Register B
Instruction constant
Incremented PC


valE
Bch
ALU result
Branch flag
Memory

valM Value from
memory
Decode § Write back
valA
valB
– 31 –
Register value A
Register value B
Processor
4.3.2， 4.3.3, 4.3.4
SEQ Operation
State


Combinational
Logic
Write
Read


Data
Data
memory
memory
 Access same memory space
 Data: for reading/writing
program data
 Instruction: for reading
instructions
CC
CC
Write
Ports
Read
Ports
Register
Register
file
file
All updated as clock rises
Combinational Logic



PC
0x00c
– 32 –
Program counter register (PC)
Condition code register (CC)
Register File
Memories
ALU
Control logic
Memory reads
 Instruction memory
 Register file
 Data memory
Processor
Figure 4.23 P297
SEQ
Operation
#2 (point 1)
Combinational
Logic
CC
CC
100
100
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Clock
Cycle 1:
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
Write
Read

Data
Data
memory
memory
Write
Ports
Read
Ports
Register
Register
file
file

state set according to
second irmovl
instruction
combinational logic
starting to react to
state changes
%ebx
0x100
%ebx == 0x100
PC
0x00c
– 33 –
Processor
SEQ
Operation
#3 (point 2)
Combinational
Logic
CC
CC
100
100
000
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Clock
Cycle 1:
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
Write
Read

Data
Data
memory
memory
Write
Ports
Read
Ports
Register
Register
file
file

state set according to
second irmovl
instruction
combinational logic
generates results for
addl instruction
%ebx
0x100
%ebx == 0x100
0x00e
PC
0x00c
– 34 –
Processor
SEQ
Operation
#4 (point 3)
Cycle 1
Cycle 3
Cycle 4
Cycle 1:
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
Read
Write

Combinational
Logic
CC
CC
000
000
Cycle 2
Clock
Data
Data
memory
memory
Read
Ports
Write
Ports
Register
Register
file
file
%ebx
%ebx == 0x300
0x300

state set
according to addl
instruction
combinational
logic starting to
react to state
changes
PC
0x00e
– 35 –
Processor
SEQ
Operation
#5 (point 4)
Cycle 1
Cycle 3
Cycle 4
Cycle 1:
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
Read
Write

Combinational
Logic
CC
CC
000
000
Cycle 2
Clock
Data
Data
memory
memory
Read
Ports
Write
Ports
Register
Register
file
file
%ebx
%ebx == 0x300
0x300

state set
according to addl
instruction
combinational
logic generates
results for je
instruction
0x013
PC
0x00e
– 36 –
Processor
SEQ Semantics
Achieve the same effect as a sequential execution of
the assignment shown in the tables of Figures 4.16
to 4.19


Though all of the state updates occur simultaneously at the
clock rises to the next cycle.
A problem: popl %esp need to sequentially write two
registers. So the register file control logic must process it.
Principle: never needs to read back the state updated
by an instruction in order to complete the processing
of this instruction (P295)



– 37 –
If so, the update must happen in the instruction cycle
E.g. pushl semantics
E.g. no one instruction need to both set and then read the
condition codes.
Processor
SEQ CPU
Implementation
– 38 –
Processor
What we will discuss today?
The implementation of a sequential CPU ---- SEQ



Every Instruction finished in one cycle.
Instruction executes in sequential
No two instruction execute in parallel or overlap
An revised version of SEQ ---- SEQ+


– 39 –
Modify the PC Update stage of SEQ
to show the difference between ISA and implementation
Processor
Some Macros
Figure 4.24 P299
– 40 –
Name
INOP
IHALT
IRRMOVL
IIRMOVL
IRMMOVL
IMRMOVL
IOPL
IJXX
…………
IPOPL
RESP
Value
0
1
2
3
4
5
6
7
……
B
6
RENONE
ALUADD
8
0
Meaning
Code for nop instruction
Code for halt instruction
Code for rrmovl instruction
Code for irmovl instruction
Code for rmmovl instruction
Code for mrmovl instruction
Code for integer op instructions
Code for jump instructions
……………………………
Code for popl instruction
Register ID for %esp
Indicates no register file access
Function for addition operationProcessor
SEQ Hardware
Structure Figure 4.20 P292
newPC
PC
valE, valM
Write back
valM
Stages

Fetch
 Read instruction from memory

Data
Data
memory
memory
Memory
Addr, Data
Decode
 Read program registers

Execute
 Compute value or address

valE
Memory
Bch
Execute
CC
CC
ALU
ALU
aluA, aluB
 Read or write data

Write Back
valA, valB
 Write program registers

PC
 Update program counter
srcA, srcB
dstA, dstB
Decode
A
B
Register
RegisterM
file
file
E
Instruction Flow



Read instruction at address
specified by PC
Process through stages
Update program counter
icode ifun
rA , rB
valC
valP
,
Fetch
Instruction
Instruction
memory
memory
PC
PC
increment
increment
PC
– 41 –
Processor
Difference between semantics and
implementation
ISA

Every stage may update some states, these updates occur
sequentially
SEQ

– 42 –
All the state update operations occur simultaneously at
clock rising (except memory and CC)
Processor
SEQ Hardware
newPC
New
PC
PC
Figure 4.21 P293
Key
valM
data out

Blue boxes:
predesigned hardware
blocks
read
write
Addr
 E.g., memories, ALU

Gray boxes:
control logic
Data
Data
memory
memory
Mem.
control
Memory
Execute
Bch
valE
CC
CC
ALU
ALU
ALU
A
Data
ALU
fun.
ALU
B
 Describe in HCL




– 43 –
White ovals (椭圆):
labels for signals
Thick lines:
32-bit word values
Thin lines:
4-8 bit values
Dotted lines:
1-bit values
valA
Decode
A
valB
dstE dstM srcA
srcB
dstE dstM srcA
srcB
B
Register
Register M
file
file
E
Write back
icode
Fetch
ifun
rA
rB
Instruction
Instruction
memory
memory
valC
valP
PC
PC
increment
increment
PC
Processor
Fetch Logic
icode
ifun
rA
rB
valC
Figure 4.25 P299
valP
Need
valC
Instr
valid
Need
regids
Split
Split
PC
PC
increment
increment
Align
Align
Byte 0
Bytes 1-5
Instruction
Instruction
memory
memory
Predefined Blocks




– 44 –
PC
PC: Register containing PC
Instruction memory: Read 6 bytes (PC to PC+5)
Split: Divide instruction byte into icode and ifun
Align: Get fields for rA, rB, and valC
Processor
Fetch Logic
icode
ifun
rA
rB
valC
valP
Need
valC
Instr
valid
Need
regids
Split
Split
PC
PC
increment
increment
Align
Align
Byte 0
Bytes 1-5
Instruction
Instruction
memory
memory
PC
Control Logic



– 45 –
Instr. Valid: Is this instruction valid?
Need regids: Does this instruction have a register
bytes?
Need valC: Does this instruction have a constant word?
Processor
Fetch Control
Logic
P300
nop
0
0
halt
1
0
rrmovl rA, rB
2
0 rA rB
irmovl V, rB
3
0
8 rB
V
rmmovl rA, D(rB)
4
0 rA rB
D
mrmovl D(rB), rA
5
0 rA rB
D
OPl rA, rB
6
fn rA rB
jXX Dest
7
fn
Dest
call Dest
8
0
Dest
ret
9
0
pushl rA
A
0 rA 8
popl rA
B
0 rA 8
bool need_regids =
icode in { IRRMOVL, IOPL, IPUSHL, IPOPL,
IIRMOVL, IRMMOVL, IMRMOVL };
bool instr_valid = icode in
{ INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL,
IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL };
– 46 –
Processor
Decode & Write-Back Logic
Figure 4.26 P300
Register File



Read ports A, B
Write ports E, M
Addresses are register IDs or
8 (no access)
valA
valB
A
B
Register
Register
file
file
dstE
dstM
srcA
dstE dstM srcA
valM valE
M
E
srcB
srcB
Control Logic


– 47 –
srcA, srcB: read port
addresses
dstA, dstB: write port
addresses
icode
rA
rB
Processor
A Source
OPl rA, rB
P301
Decode
valA  R[rA]
Read operand A
rmmovl rA, D(rB)
Decode
valA  R[rA]
Read operand A
popl rA
Decode
valA  R[%esp]
Read stack pointer
jXX Dest
Decode
No operand
call Dest
Decode
No operand
ret
Decode
valA  R[%esp]
Read stack pointer
int srcA = [
icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL
icode in { IPOPL, IRET } : RESP;
1 : RNONE; # Don't need register
];
– 48 –
} : rA;
Processor
E Destination
P301
OPl rA, rB
Write-back R[rB]  valE
Write back result
rmmovl rA, D(rB)
Write-back
None
popl rA
Write-back R[%esp]  valE
Update stack pointer
jXX Dest
Write-back
None
call Dest
Write-back R[%esp]  valE
Update stack pointer
ret
Write-back R[%esp]  valE
Update stack pointer
int dstE = [
icode in { IRRMOVL, IIRMOVL, IOPL} : rB;
icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP;
1 : RNONE; # Don't need register
];
– 49 –
Processor
Execute Logic
Figure 4.27 P302
Units

ALU
 Implements 4 required functions
 Generates condition code values

Bch
CC
 Register with 3 condition code
bcond
bcond
bits

valE
CC
CC
bcond
ALU
fun.
ALU
ALU
 Computes branch flag
Set
CC
Control Logic




– 50 –
Set CC: Should condition code
register be loaded?
ALU A: Input A to ALU
ALU B: Input B to ALU
icode ifun
ALU
A
valC
ALU
B
valA
valB
ALU fun: What function should
ALU compute?
Processor
ALU A Input
P302
Execute
OPl rA, rB
valE  valB OP valA
Perform ALU operation
rmmovl rA, D(rB)
Execute
valE  valB + valC
Compute effective address
popl rA
Execute
valE  valB + 4
Increment stack pointer
jXX Dest
Execute
No operation
call Dest
Execute
valE  valB + –4
Decrement stack pointer
ret
Execute
valE  valB + 4
Increment stack pointer
int aluA = [
icode in { IRRMOVL, IOPL } : valA;
icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valC;
icode in { ICALL, IPUSHL } : -4;
icode in { IRET, IPOPL } : 4;
# Other instructions don't need ALU
– 51 –
];
Processor
ALU Operation
OPl rA, rB
P303
Execute
valE  valB OP valA
Perform ALU operation
rmmovl rA, D(rB)
Execute
valE  valB + valC
Compute effective address
popl rA
Execute
valE  valB + 4
Increment stack pointer
jXX Dest
Execute
No operation
call Dest
Execute
valE  valB + –4
Decrement stack pointer
ret
Execute
– 52 –
valE  valB + 4
int alufun = [
icode == IOPL : ifun;
1 : ALUADD;
];
Increment stack pointer
Processor
Condition Set
P303
Bool set_cc = icode in { IOPL };
We will not discuss the detail of Bcond

– 53 –
Though it is also a control unit
Processor
Memory Logic
Figure 4.28 P303
Memory

valM
Reads or writes memory
word
data out
Mem.
read
Mem.
write
Control Logic




– 54 –
Mem. read: should word be
read?
Mem. write: should word be
written?
Mem. addr.: Select address
Mem. data.: Select data
read
Data
Data
memory
memory
write
data in
Mem
addr
icode
valE
Mem
data
valA valP
Processor
Memory Address
P304
OPl rA, rB
Memory
No operation
rmmovl rA, D(rB)
Memory
M4[valE]  valA
Write value to memory
popl rA
Memory
valM  M4[valA]
Read from stack
jXX Dest
Memory
No operation
call Dest
Memory
M4[valE]  valP
Write return value on stack
ret
Memory
valM  M4[valA]
Read return address
int mem_addr = [
icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : valE;
icode in { IPOPL, IRET } : valA;
# Other instructions don't need address
Processor
– 55 – ];
Memory Read
P304
OPl rA, rB
Memory
No operation
rmmovl rA, D(rB)
Memory
M4[valE]  valA
Write value to memory
popl rA
Memory
valM  M4[valA]
Read from stack
jXX Dest
Memory
No operation
call Dest
Memory
M4[valE]  valP
Write return value on stack
ret
Memory
valM  M4[valA]
Read return address
bool mem_read = icode in { IMRMOVL, IPOPL, IRET };
bool mem_write = icode in { IRMMOVL, IPUSHL, ICALL };
– 56 –
Processor
PC Update Logic
Figure 4.29 P304
PC
New PC

New
PC
Select next value of PC
icode
– 57 –
Bch
valC
valM
valP
Processor
PC
Update
P304
OPl rA, rB
PC update
PC  valP
Update PC
rmmovl rA, D(rB)
PC update
PC  valP
Update PC
popl rA
PC update
PC  valP
Update PC
jXX Dest
PC update
PC  Bch ? valC : valP
Update PC
call Dest
PC update
PC  valC
Set PC to destination
ret
PC update
– 58 –
PC  valM
Set PC to return address
int new_pc = [
icode == ICALL : valC;
icode == IJXX && Bch : valC;
icode == IRET : valM;
1 : valP;
];
Processor
SEQ Hardware
(Review)


Stages occur in sequence
One operation in process
at a time
newPC
New
PC
PC
valM
data out
read
Data
Data
memory
memory
Mem.
control
Memory
write
Addr
Figure 4.21 P293
Execute
Bch
valE
CC
CC
ALU
ALU
ALU
A
Data
ALU
fun.
ALU
B
valA
Decode
A
valB
dstE dstM srcA
srcB
dstE dstM srcA
srcB
B
Register
Register M
file
file
E
Write back
icode
Fetch
ifun
rA
rB
Instruction
Instruction
memory
memory
valC
valP
PC
PC
increment
increment
PC
– 59 –
Processor
4.3.5
SEQ+ Hardware
valM
data out
read
Data
Data
memory
memory
Mem.
control
Memory
write
Addr


Still sequential
implementation
Reorder PC stage to put at
beginning
Execute
Bch
valE
CC
CC
ALU
ALU
ALU
A
Data
ALU
fun.
ALU
B
PC Stage


Task is to select PC for
current instruction
Based on results
computed by previous
instruction
Processor State


– 60 –
PC is no longer stored in
register
But, can determine PC
based on other stored
information
valA
Decode
valB
A
dstE dstM srcA
srcB
dstE dstM srcA
srcB
B
Register
Register M
file
file E
Write back
icode
Fetch
ifun
rA
rB
valC
Instruction
Instruction
memory
memory
valP
PC
PC
increment
increment
PC
PC
PC
pIcode pBch
pValM
pValC
pValP
Processor
PC Computation
P308
Int pc= [
pIcode == ICALL : pValC;
pIcode == IJXX && bBch : pValC;
PIcode == IRET : pValM;
1 : pValP;
];
– 61 –
Processor
SEQ Summary
Implementation




Express every instruction as series of simple steps
Follow same general flow for each instruction type
Assemble registers, memories, predesigned combinational
blocks
Connect with control logic
Limitations




– 62 –
Too slow to be practical
In one cycle, must propagate through instruction memory,
register file, ALU, and data memory
Would need to run clock very slowly
Hardware units only active for fraction of clock cycle
Processor