An Efficient Test Relaxation
Technique for Combinational &
Full-Scan Sequential Circuits
Aiman El-Maleh, Ali Alsuwaiyan
King Fahd University of Petroleum & Minerals,
Dept. of Computer Eng., Saudi Arabia
Outline

Introduction

Problem definition

Illustrative example

Proposed relaxation algorithm

Experimental results

Improving the effectiveness of test compaction &
compression

Conclusion
2
Introduction

With today’s technology, complete systems with
millions of transistors are built on a single chip.

Increasing complexity of systems-on-a-chip and its
test data size increased cost of testing.

Test data must be stored in tester memory and
transferred from tester to chip.

Cost of automatic test equipment increases with
increase in speed, channel capacity, and memory.

Need for test data reduction is imperative.
3
• Test compaction.
• Test compression.
Introduction

Effectiveness of test compaction and compression
techniques can improve significantly if a partially
specified (relaxed) test set is provided.

Most compression techniques assume a relaxed test.

Compaction achieved by test vector merging of
compatible vectors.

Test relaxation can improve effectiveness of dynamic
test compaction by taking advantage of random test
pattern generation.

Test relaxation can also help in test power reduction
• Specify relaxed bits to reduce number of transitions during
scan.
4
Problem Definition

Given a test set of a given combinational or full-scan
circuit, generate a partially specified test set that
maintains the same fault coverage while maximizing
the number of unspecified bits i.e., Xs.

Test relaxation problem has not been solved
effectively in literature.

A test set can be relaxed using a brute-force method
• Every bit is tested for possibility of changing it to x by fault
•

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simulation.
Impractical for large circuits.
Dynamic compaction does not relax an already
existing test set.
Illustrative Example
x0
A
B 0
0/1
0/1
0
0/0
0/x
G1
G6
0/1
0
G4
1/0
1
0
C
1
1/x
1/0
1
B stuck-at-1
Fault
excitation
0
1/0
G5
0
D
0
E
0
0
G3
Fault
propagation
G2
To guarantee stem faults propagation, never justify a
controlling value from a reachable line.
From this example, we conclude that we need to
B=0 satisfiedG3=0 implies C=0, DE=XX OR C=X, DE=00
identify reachable lines before justification.
Thus, to guarantee fault detection, G1=0 implies A=0
Apparently, G1=0 satisfied and thus A=X (WRONG!!)
(Because A is unreachable).
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Proposed Technique
For every test vector t do
Fault simulate the circuit under the test t
For every newly detected fault f do
BuildRequirementList( f ) /**** Returns L ****/
For every line j in L do
justify( j )
End for
Mark all lines as unreachable
End for
Output relaxed vector
Mark all lines as non-required
End for
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Proposed Technique

Definition: A line l is said to be reachable from a stem
s if the fault effect in stem s reaches line l.

BuildRequirementList ( f ):
• Assume the faulty line is j.
• Adds j to L (fault activation).
• Trace j forward until a fanout stem s is reached and add
•
•
8
all side inputs of traced path to L.
Mark reachable lines from s until an output is reached.
Trace backward from the reached output to the stem
and add all side inputs of reachable lines to L.
Proposed Technique

9
Justification of a line J , justify( J ):
Case
Action
J is a NOT, XOR, XNOR
Justify all inputs of J
J has a non-cont. value
Justify all inputs of J
There is an unreachable
input K with cont. value
Justify K
Otherwise
Justify all inputs of J
Selection Criteria

Justification of a controlling value may involve some
selection.

Cost functions are employed to minimize the number
of specified inputs.

Regular cost functions used in ATPG can b e used
• don’t take advantage of the fact that a stem can justify
several required values.

10
Fanout-based cost functions are proposed to take
advantage of this fact.
Selection Criteria

For an AND gate, fanout-based cost functions are
computed as follows:
• Let l be the output of AND gate with i inputs.
• Let F(l) denote the the fanout (i.e. the number of fanout
•
branches) of line l.
0-controllability of line l:
C0 l  
min C0 (i )
i
F (l )
• 1-controllability of line l:
C1 (l ) 
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 C (i)
1
i
F (l )
Selection Criteria - Example
RC0(C)=1 RC0(G1)=1
FC0(C)=1/2 FC0(G1)=1/2
B
C
D
0
G1
0
0
0
RC0(G3)=2
FC0(G3)=1
G3
G2
E
F
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G4
1
G6
0
1
0
0
G5
0
0
A
To detect fault
A s-a-0
value G5=0 is
required
RC0(G4)=2
FC0(G4)=2
0
RC0(G2)=1
FC0(G2)=1/2
Based
on G5=0,
regular
cost G3=0
functions,
either
To
justify
either
orfunctions,
G4=0
Based
on fanout-based
cost
G3 or G4
could be selected, which may
could
bebe
selected.
G3 will
selected, which results in
result in two required values.
one required value C=0.
Selection Criteria

In general, fanout-based cost functions provide better
selection criteria than regular cost functions.

There are situations where regular cost functions
provide better selection criteria.

To take advantage of both, a weighted selection
criteria is used
C0 (l )  A  RC 0 (l )  B  FC0 (l )
C1 (l )  A  RC1 (l )  B  FC1 (l )
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Experimental Results

ISCAS 85 and full-scan versions of ISCAS 89.

SUN Ultra60, 450 MHZ, RAM=512 MB.

Used test sets are highly compacted and are
generated by MinTest [Hamzaoglu et al., ICCAD 98].

Compare our results with a brute-force relaxation
method.

Effect of selection criteria on test relaxation.

Impact of test relaxation on test data compression
based on FDR codes [Chandra et al., VTS 2001].

Impact of test relaxation on test compaction by vector
merging.
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Percentage of Xs
Average Xs = 68.3% (brute-force).
 Average Xs = 65.4% (proposed).
 An average difference of only 2.9%.

15
Test Relaxation CPU Time
Average CPU Time = 152725 Seconds (brute-force).
 Average CPU Time = 6 Seconds (proposed).

16
Cost Function Effect on Extracted
Percentage of Xs
Circuit
c5315
A=0
B=0
48.527
A=1
B=0
50.076
A=0
B=1
52.065
A=1
B=1
52.080
A=1
B=2
52.080
A=1
B=6
52.080
c7552
48.091
48.329
52.068
52.075
52.075
52.075
c2670
65.899
66.407
68.377
68.748
68.748
68.767
s5378
68.422
69.891
71.057
70.484
70.484
70.753
S9234.1
63.621
64.372
65.949
66.046
66.046
66.408
S15850.1
S13207.1
S38584.1
s38417
s35932
Average
77.693
92.457
75.328
65.518
22.986
62.854
77.855
92.485
75.839
65.865
28.120
63.924
78.971
92.920
78.072
66.467
27.415
65.336
78.391
92.920
77.794
66.162
28.238
65.294
78.448
92.925
77.795
66.164
28.238
65.300
78.830
92.928
77.951
66.171
28.238
65.420
17
Impact of Test Relaxation on FDR
Compression
18
Impact of Test Relaxation on
Compaction by Vector Merging
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Conclusion

A novel and efficient test relaxation technique has
been presented.

New selection cost functions proposed to maximize
number of Xs.

While achieving slightly less test relaxation quality
than brute-force test relaxation, the technique is
faster by several orders of magnitude.

Demonstrated the impact of test relaxation in
improving the effectiveness of test compaction and
compression techniques.
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