ECE 4110– Digital Logic Design
Lecture #25
•
Agenda
1. More on State Machines in VHDL
•
Announcements
1. HW #11 due.
2. HW #12 assigned.
Lecture #25
Page 1
State Machines in VHDL
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Next State Logic “F”
- we use another process to construct “F”
Lecture #25
Page 2
State Machines in VHDL
•
Next State Logic “F”
- the process will be combinational logic
NEXT_STATE_LOGIC : process (In, Current_State)
begin
case (Current_State) is
when S0 => if
elsif
when S1 => if
elsif
when S2 => if
elsif
when S3 => if
elsif
(In=‘0’) then
(In=‘1’) then
(In=‘0’) then
(In=‘1’) then
(In=‘0’) then
(In=‘1’) then
(In=‘0’) then
(In=‘1’) then
Next_State <= S0;
Next_State <= S1; end if;
Next_State <= S2;
Next_State <= S0; end if;
Next_State <= S0;
Next_State <= S3; end if;
Next_State <= S0;
Next_State <= S0; end if;
end case;
end process;
Lecture #25
Page 3
State Machines in VHDL
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Output Logic “G”
- we use another process to construct “G”
- the expressions in the sensitivity list dictate Mealy/Moore type outputs
- for now, let’s use combinational logic for G (we’ll go sequential later)
Lecture #25
Page 4
State Machines in VHDL
•
Output Logic “G”
- Mealy type outputs
OUTPUT_LOGIC : process (In, Current_State)
begin
case (Current_State) is
when S0 => if
elsif
when S1 => if
elsif
when S2 => if
elsif
when S3 => if
elsif
(In=‘0’) then
(In=‘1’) then
(In=‘0’) then
(In=‘1’) then
(In=‘0’) then
(In=‘1’) then
(In=‘0’) then
(In=‘1’) then
Found <= 0;
Found <= 0; end if;
Found <= 0;
Found <= 0; end if;
Found <= 0;
Found <= 0; end if;
Found <= 0;
Found <= 1; end if;
end case;
end process;
Lecture #25
Page 5
State Machines in VHDL
•
Output Logic “G”
- Moore type outputs
OUTPUT_LOGIC : process (Current_State)
begin
case (Current_State) is
when S0 => Found <= 0;
when S1 => Found <= 0;
when S2 => Found <= 0;
when S3 => Found <= 1;
end case;
end process;
- this is just an example, it doesn’t really work for this machine
Lecture #25
Page 6
State Machines in VHDL
•
Example
- Let’s design a 2-bit Up/Down Gray Code Counter using User-Enumerated State Encoding
- In=0, Count Up
- In=1, Count Down
- this will be a Moore Type Machine
- no Reset
Lecture #25
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State Machines in VHDL
•
Example
- let’s collect our thoughts using a State/Output Table
Current_State
In
Next_State
Out
CNT0
0
1
0
1
0
1
0
1
CNT1
CNT3
CNT2
CNT0
CNT3
CNT1
CNT0
CNT2
00
CNT1
CNT2
CNT3
01
11
10
Lecture #25
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State Machines in VHDL
•
Example
architecture CNT_arch of CNT is
type State_Type is (CNT0, CNT1, CNT2, CNT3);
signal Current_State, Next_State : State_Type;
begin
STATE_MEMORY : process (CLK)
begin
if (CLK’event and CLK='1') then
Current_State <= Next_State;
end if;
end process;
NEXT_STATE_LOGIC : process (In, Current_State)
begin
case (Current_State) is
when CNT0 => if
elsif
when CNT1 => if
elsif
when CNT2 => if
elsif
when CNT3 => if
elsif
end case;
end process;
(In=‘0’) then
(In=‘1’) then
(In=‘0’) then
(In=‘1’) then
(In=‘0’) then
(In=‘1’) then
(In=‘0’) then
(In=‘1’) then
Next_State
Next_State
Next_State
Next_State
Next_State
Next_State
Next_State
Next_State
<= CNT1;
<= CNT3; end if;
<= CNT2;
<= CNT0; end if;
<= CNT3;
<= CNT1; end if;
<= CNT0;
<= CNT2; end if;
OUTPUT_LOGIC : process (Current_State)
begin
case (Current_State) is
when CNT0 => Out <= “00”;
when CNT1 => Out <= “01”;
when CNT2 => Out <= “11”;
when CNT3 => Out <= “10”;
end case;
end process;
end architecture;
Lecture #25
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State Machines in VHDL
•
Example
- in the lab, we may want to observe the states on the LEDs
- in this case we want to explicitly encode the STATE variables
architecture CNT_arch of CNT is
subtype State_Type is BIT_VECTOR (1 dowto 0);
constant CNT0 : State_Type := “00”;
constant CNT1 : State_Type := “01”;
constant CNT2 : State_Type := “10”;
constant CNT3 : State_Type := “11”;
signal Current_State, Next_State : State_Type;
Lecture #25
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