DCE Unit-3:
Half Adder, Full Adder, Binary Adder-Subtractor, Multiplexers
HALF ADDER
Half Adder is a combinational circuit which can add two bits (i.e., two one-bit (single-bit)
binary numbers).
The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C).
[The carry signal represents an overflow into the next digit of a multi-digit addition.]
[The half adder adds two input bits and generates a carry and sum, which are the two outputs of a
half adder. The input variables of a half adder are called the augend and addend bits. The output
variables are the sum and carry.]
Truth Table: The truth table for the half adder is:
Inputs Outputs
A
B
C
S
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
o The sum column resembles like an output of the XOR gate.
o The carry column resembles like an output of the AND gate.
Circuit
Cases
1. When A=0 and B=0, the XOR gate gives sum output as 0 (as number of 1’s
are even) and AND gate also gives carry output as 0.
2. When A=0 and B=1, the XOR gate gives sum output as 1 (as number of 1’s
are odd) and AND gate gives carry output as 0.
3. When A=1 and B=0, the XOR gate gives sum output as 1 (as number of 1’s
are odd) and AND gate gives carry output as 0.
4. When A=1 and B=1, the XOR gate gives sum output as 0 (as number of 1’s
are even) and AND gate gives carry output as 1.
More Explanation
With the help of half adder, we can design circuits that are capable of performing simple addition with
the help of logic gates.
Let us first take a look at the addition of single bits.
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 10
These are the least possible single-bit combinations. But the result for 1+1 is 10. Though this problem
can be solved with the help of an EXOR Gate, if you do care about the output, the sum result must be
re-written as a 2-bit output.
Thus the above equations can be written as
0+0 = 00
0+1 = 01
1+0 = 01
1+1 = 10
Here the output ‘1’of ‘10’ becomes the carry-out. The result is shown in a truth-table below. ‘SUM’ is
the normal output and ‘CARRY’ is the carry-out.
INPUTS
A
0
0
1
1
B
0
1
0
1
OUTPUTS
SUM
CARRY
0
0
1
0
1
0
0
1
From the equation it is clear that this 1-bit adder can be easily implemented with the help of EXOR
Gate for the output ‘SUM’ and an AND Gate for the carry. Take a look at the implementation below.
FULL ADDER
Limitations (disadvantages) of half-adder
In multi-digit addition we have to add two bits along with the carry of previous digit addition. Such
addition requires addition of 3 bits. This is not possible in half-adders.
In a full adder, three bits can be added at a time. The third bit is a carry from a less significant column.
Truth Table
Full Adder Equation
 Sum = A XOR B XOR C
 Carry = AB + BC + CA
Circuit
Cases
1. When A=0, B=0 and Cin=0, three AND gates gives output as (0,0,0) and hence carry from OR
gate is 0; the XOR gives sum output 0 (as numbers of 1’a are even).
2. When A=0, B=0 and Cin=1, three AND gates gives output as (0,0,0) and hence carry from OR
gate carry is 0; the XOR gives sum output 1 (as numbers of 1’a are odd).
3. When A=0, B=1 and Cin=0, three AND gates gives output as (0,0,0) and hence carry from OR
gate carry is 0; the XOR gives sum output 1 (as numbers of 1’a are odd).
4. When A=0, B=1 and Cin=1, three AND gates gives output as (0,0,1) and hence carry from OR
gate carry is 1; the XOR gives sum output 0 (as numbers of 1’a are even).
5. When A=1, B=0 and Cin=0, three AND gates gives output as (0,0,0) and hence carry from OR
gate carry is 0; the XOR gives sum output 1 (as numbers of 1’a are odd).
6. When A=1, B=0 and Cin=1, three AND gates gives output as (0,1,0) and hence carry from OR
gate carry is 1; the XOR gives sum output 0 (as numbers of 1’a are even).
7. When A=1, B=1 and Cin=0, three AND gates gives output as (0,0,1) and hence carry from OR
gate carry is 1; the XOR gives sum output 0 (as numbers of 1’a are even).
8. When A=1, B=1 and Cin=1, three AND gates gives output as (1,1,1) and hence carry from OR
gate carry is 1; the XOR gives sum output 1 (as numbers of 1’a are odd).
Block Diagram
Alternate Representation of Full-Adder
BINARY ADDER-SUBTRACTOR
o While we add the LSB, there is no carry to be handled and thus, only a half
adder is used for this stage.
o For any other bit addition, there may be a carry from the preceding stage and
thus, full adders are used for these stages.
o Example: 9 + 5
o A3A2A1A0 =1001 and B3B2B1B0 = 0101
o Let S = Sub = 0 (for Addition)
o First FA adds three bits: Output of first XOR, A0, and S; and gives sum as
S0 and carry C1.
o First XOR (from right) gets input 1 and 0, which give output 1. That
is, same as B0. If S=0, all XOR will pass all B bits as it is, and if S=1,
then it will invert all the B bits (gives once complement of B).
Additionally, it adds one more 1 bit to convert B in to its 2’s
complement.
o The second FA adds 3 bits: output of second XOR, A1, and C1; and gives
sum S1 and carry C2
o
o Similarly, third FA adds 3 bits: output of third XOR, A2, and C2; and gives
sum S2 and carry C3
o
o Finally, forth FA adds 3 bits: output of forth third XOR, A3, and C3; and
gives sum S3 and carry C4
o
o Thus, final answer is formed as C4S3S2S1S0
o
MULTIPLEXER
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A multiplexer (or mux) is a combinational logic circuit (device) that selects one of
several input signals and forwards the selected input into a single line.
A 2n-to-1 multiplexer has 2n input data lines and n input selection lines whose bit combinations
determine which input data are selected. That is, the selection of particular input data line for
the output is determined by a set of selection input.
A multiplexer is also called a Data Selector.
A multiplexer is a combinational circuit that receives binary information from of 2n input data
lines and directs it to a single output line.
A 4-to-1 line multiplexer is shown below. Each of the four data inputs I0 to I3 is applied to one
input of an AND gate.
A (4-to-1) multiplexer of 22 inputs has 2 select lines, which are used to select which input
line (out of 4) to send to the output.
Figure: 4-to-1 Multiplexer
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The two selection inputs S0 and S1 are decoded to select particular AND gate. The output of
AND gates are applied to a single OR gate to provide the single output.
When the selection inputs are equal to 00, output Y is equal to input I0. When the selection
inputs are equal to 01, input I1 has path to output, and similarly for the other two combinations.
Truth Table
Selection Line
S1
S0
0
0
0
1
1
0
1
1
Output
Y
I0
I1
I2
I3
Figure: 8-to-s1 Multiplexer